专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06004862A Core array and periphery isolation technique 失效
标题翻译：核心阵列和外围隔离技术
公开(公告)号：US06004862A
公开(公告)日：1999-12-21
申请号：US8320
申请日：1998-01-20
申请人： Unsoon Kim , Hung-Sheng Chen , Kashmir Sahota , Yu Sun
发明人： Unsoon Kim , Hung-Sheng Chen , Kashmir Sahota , Yu Sun
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/76224
摘要： A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to the core area, comprising the steps of: forming a first layer of first insulator material above a semiconductor substrate having a core area and a periphery area, wherein the first insulator material constitutes a polish stop for polishing processes and also as an oxidation barrier; patterning the first layer of first insulator material to expose first portions of the semiconductor substrate substantially only in the core area while using the first insulator material to substantially mask the periphery area; forming a plurality of trenches into the exposed first portions of semiconductor substrate in the core area; filling the plurality of trenches with an insulator; polishing down to the first layer of first insulator material; removing the first layer of first insulator material; forming a second layer of first insulator material over the core and periphery areas; forming openings down into the second layer of first insulator material to expose second portions of the semiconductor substrate substantially only in the periphery area while using the second layer to substantially mask the core area; and forming an isolation region in the exposed second portions of the semiconductor substrate.
摘要翻译：一种用于形成半导体集成电路的方法，所述半导体集成电路具有密集地填充有有源器件的核心区域，并且与所述核心区域相比具有较少密集地填充有源器件的外围区域，包括以下步骤：在第一绝缘体材料的上方形成第一层具有芯区域和周边区域的半导体衬底，其中所述第一绝缘体材料构成用于抛光工艺的抛光止挡件以及氧化屏障; 图案化第一绝缘体材料层，以在使用第一绝缘体材料基本上遮蔽周边区域的同时，在半导体衬底的基本上仅在芯部区域露出第一部分; 在芯区域中的半导体衬底的暴露的第一部分中形成多个沟槽; 用绝缘体填充多个沟槽; 抛光到第一绝缘体材料层; 去除第一绝缘体材料的第一层; 在所述芯和外围区域上形成第二绝缘体材料层; 将第一绝缘体材料的第二层向下形成开口，以便在使用第二层基本上掩蔽核心区域时，基本上只在周边区域露出半导体衬底的第二部分; 以及在半导体衬底的暴露的第二部分中形成隔离区。

2. 发明授权

US6124640A Scalable and reliable integrated circuit inter-level dielectric 有权
标题翻译：可扩展和可靠的集成电路级间电介质
公开(公告)号：US6124640A
公开(公告)日：2000-09-26
申请号：US144506
申请日：1998-08-31
申请人： Kashmir Sahota , Richard J. Huang , Hung-Sheng Chen , Yu Sun
发明人： Kashmir Sahota , Richard J. Huang , Hung-Sheng Chen , Yu Sun
IPC分类号： H01L21/3105 , H01L21/314 , H01L21/316 , H01L21/768 , H01L51/00
CPC分类号： H01L21/76837 , H01L21/76834 , H01L21/31051 , H01L21/3145 , H01L21/31612
摘要： An inter-level dielectric (ILD) is formed from a lower barrier layer comprising a conformal silicon oxynitride layer, a gap fill layer comprising a high-density plasma (HDP) oxide and a cap layer. The use of HDP oxide as a gap fill layer enables better control of the ILD thickness, avoids outgasing problems, facilitates via formation and reduces planarization.
摘要翻译：层间电介质（ILD）由包括保形氮氧化硅层的下阻挡层，包含高密度等离子体（HDP）氧化物和盖层的间隙填充层形成。使用HDP氧化物作为间隙填充层能够更好地控制ILD厚度，避免出现问题，便于通孔形成并减少平坦化。

3. 发明申请

US20060223278A1 Non-critical complementary masking method for poly-1 definition in flash memory device fabrication 有权
标题翻译：闪存器件制造中poly-1定义的非关键互补掩模方法
公开(公告)号：US20060223278A1
公开(公告)日：2006-10-05
申请号：US11099339
申请日：2005-04-04
申请人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher Raeder , Christopher Foster , Harpreet Sachar , Kashmir Sahota
发明人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher Raeder , Christopher Foster , Harpreet Sachar , Kashmir Sahota
IPC分类号： H01L21/76
CPC分类号： H01L27/105 , H01L21/3212 , H01L21/32139 , H01L21/76229 , H01L27/1052 , H01L27/11526 , H01L27/11543 , H01L27/11568
摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.
摘要翻译：公开了一种用于在半导体晶片中定义多晶硅层的方法。使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。

4. 发明授权

US07294573B1 Method for controlling poly 1 thickness and uniformity in a memory array fabrication process 有权
标题翻译：用于控制存储器阵列制造工艺中聚1厚度和均匀性的方法
公开(公告)号：US07294573B1
公开(公告)日：2007-11-13
申请号：US11035188
申请日：2005-01-13
申请人： Krishnashree Achuthan , Unsoon Kim , Kashmir Sahota , Patriz C. Regalado
发明人： Krishnashree Achuthan , Unsoon Kim , Kashmir Sahota , Patriz C. Regalado
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/7684
摘要： According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate.
摘要翻译：根据一个示例性实施例，一种方法包括将位于衬底上的场氧化物区域上的多晶硅层平坦化以形成多晶硅段，其中多晶硅段具有与场氧化物区域的顶表面基本上平面的顶表面，场氧化物区域具有第一高度，并且多晶硅段具有第一厚度。该方法还包括在衬底的周边区域上去除硬掩模。根据该示例性实施例，该方法还包括蚀刻多晶硅段以使多晶硅段具有第二厚度，这导致多晶硅段的顶表面位于场氧化物区的顶表面之下。可以通过使用湿蚀刻工艺来蚀刻多晶硅段。多晶硅段位于衬底的芯区域中。

5. 发明授权

US06133619A Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics 有权
标题翻译：集成电路级间介质中氮氧化硅薄膜的分层还原
公开(公告)号：US06133619A
公开(公告)日：2000-10-17
申请号：US144521
申请日：1998-08-31
申请人： Kashmir Sahota , Richard J. Huang , David Matsumoto , Mark T. Ramsbey , Yu Sun , Judith Quan Rizzuto
发明人： Kashmir Sahota , Richard J. Huang , David Matsumoto , Mark T. Ramsbey , Yu Sun , Judith Quan Rizzuto
IPC分类号： H01L21/312 , H01L21/314 , H01L21/768 , H01L51/00
CPC分类号： H01L21/76801 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/3124 , H01L21/3145
摘要： Outgassing from a dielectric gap fill layer, e.g., a low dielectric constant material such as HSQ, and attendant deformation or delamination of a barrier dielectric layer on an overlying patterned conductive layer during subsequent thermal processing are avoided or significantly reduced by controlling the thickness of the dielectric cap layer on the dielectric gap fill layer. Embodiments include depositing a conformal SiON barrier on a first conductive pattern, depositing a HSQ gap fill layer on the conformal SiON barrier layer, depositing a silicon oxide cap layer and planarizing such that the thickness of the planarized silicon cap layer is at least 2500 .ANG., thereby avoiding deformation and/or delamination of a conformal SiON barrier layer on an overlying patterned conductive layer during subsequent thermal processing.
摘要翻译：从介电间隙填充层，例如低介电常数材料（例如HSQ）以及随后的热处理过程中覆盖的图案化导电层上的阻挡介电层的伴随变形或分层的脱气被避免或显着减少，通过控制电介质间隙填充层上的介电覆盖层。实施例包括在第一导电图案上沉积保形SiON阻挡层，在保形SiON阻挡层上沉积HSQ间隙填充层，沉积氧化硅覆盖层并进行平坦化，使得平坦化硅覆盖层的厚度为至少2500，从而避免在随后的热处理期间覆盖的图案化导电层上的保形SiON阻挡层的变形和/或分层。

6. 发明授权

US06359307B1 Method for forming self-aligned contacts and interconnection lines using dual damascene techniques 有权
标题翻译：使用双镶嵌技术形成自对准触点和互连线的方法
公开(公告)号：US06359307B1
公开(公告)日：2002-03-19
申请号：US09493436
申请日：2000-01-29
申请人： Fei Wang , Hiroyuki Kinoshita , Kashmir Sahota , Yu Sun , Wenge Yang
发明人： Fei Wang , Hiroyuki Kinoshita , Kashmir Sahota , Yu Sun , Wenge Yang
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L23/485 , H01L27/115 , H01L27/11521 , H01L2924/0002 , H01L2924/3011 , Y02P80/30 , H01L2924/00
摘要： The present invention further provides a method for forming self-aligned contacts using a dual damascene techniques that reduces the number of process steps and results in a reduction in cycle time, cost and yield loss. In a preferred embodiment, a method for forming a contact and a channel in a dielectric layer over a region on a semiconductor substrate is provided. The contact is self-aligned. The contact and channel are formed by (1) forming a contact opening in the dielectric layer, (2) forming a channel opening in the dielectric layer, wherein the channel opening encompasses the contact opening, (3) extending the contact opening to expose a portion of the region on the semiconductor substrate; and (4) filling the contact opening and the channel opening with a conductive material to form a contact and a channel, respectively.
摘要翻译：本发明还提供了一种使用双镶嵌技术形成自对准接触的方法，其减少了工艺步骤的数量并导致了循环时间，成本和屈服损失的降低。在优选实施例中，提供了在半导体衬底上的区域上形成电介质层中的接触和沟道的方法。联系人自行对齐。接触和通道由（1）在电介质层中形成接触开口形成，（2）在电介质层中形成通道开口，其中通道开口包围接触开口，（3）延伸接触开口以露出所述半导体衬底上的所述区域的部分; 和（4）分别用导电材料填充接触开口和通道开口以形成接触和通道。

7. 发明授权

US08202779B2 Methods for forming a memory cell having a top oxide spacer 有权
标题翻译：形成具有顶部氧化物间隔物的存储单元的方法
公开(公告)号：US08202779B2
公开(公告)日：2012-06-19
申请号：US12891310
申请日：2010-09-27
申请人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
发明人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/792
摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
摘要翻译：公开了制造具有间隔层的半导体存储单元的方法。一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

8. 发明授权

US07358191B1 Method for decreasing sheet resistivity variations of an interconnect metal layer 有权
标题翻译：降低互连金属层的薄层电阻率变化的方法
公开(公告)号：US07358191B1
公开(公告)日：2008-04-15
申请号：US11388390
申请日：2006-03-24
申请人： Krishnashree Achuthan , Brad Davis , James Xie , Kashmir Sahota
发明人： Krishnashree Achuthan , Brad Davis , James Xie , Kashmir Sahota
IPC分类号： H01L21/311
CPC分类号： H01L21/3212 , H01L21/7684
摘要： According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.
摘要翻译：根据一个示例性实施例，一种方法包括在电介质层中形成多个沟槽的步骤，其中电介质层位于晶片之上。该方法还包括在电介质层上和沟槽中形成金属层，使得金属层在晶片上具有圆顶形轮廓。该方法还包括执行平面化处理以形成多个互连线，其中每个互连线位于沟槽中的一个中。在执行平坦化处理之后，金属层的圆顶形轮廓使得互连线在晶片上具有减小的厚度变化。互连线位于互连金属层中，其中金属层的圆顶形轮廓使得互连金属层在执行平坦化处理之后在晶片上具有增加的片电阻率均匀性。

9. 发明授权

US06376389B1 Method for eliminating anti-reflective coating in semiconductors 有权
标题翻译：消除半导体抗反射涂层的方法
公开(公告)号：US06376389B1
公开(公告)日：2002-04-23
申请号：US09588117
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
发明人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
IPC分类号： H01L2100
CPC分类号： H01L21/76802 , H01L21/76895 , H01L23/522 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor device without the use of an anti-reflective coating. In one embodiment, electrical devices are formed on a semiconductor substrate. A material with a low dielectric constant such as an oxide is then deposited. The low dielectric layer is then covered with photoresist and photolithographically processed and subsequently developed. The low dielectric layer is then etched using the pattern formed on the photoresist and the photoresist is later removed. Because this process works in any similar circumstances, good examples of its application are the formation of both contacts and local interconnects.
摘要翻译：本发明提供一种不使用抗反射涂层的半导体器件的制造方法。在一个实施例中，电子器件形成在半导体衬底上。然后沉积具有低介电常数的材料，例如氧化物。然后用光致抗蚀剂覆盖低介电层，并进行光刻处理并随后显影。然后使用形成在光致抗蚀剂上的图案蚀刻低介电层，随后去除光致抗蚀剂。因为这个过程在任何类似的情况下都可以工作，它的应用的很好的例子是形成两个触点和局部互连。

10. 发明授权

US06613646B1 Methods for reduced trench isolation step height 有权
标题翻译：减少沟槽隔离台阶的方法
公开(公告)号：US06613646B1
公开(公告)日：2003-09-02
申请号：US10106005
申请日：2002-03-25
申请人： Kashmir Sahota , Krishnashree Achuthan
发明人： Kashmir Sahota , Krishnashree Achuthan
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/31053
摘要： Shallow trench isolation techniques are disclosed in which a thin nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor substrate, which is then filled. The wafer is then planarized using a fixed-abrasive CMP process to mitigate or avoid step height in the shallow trench isolation process. The nitride layer is then removed following planarization.
摘要翻译：公开了一种浅沟槽隔离技术，其中在半导体衬底上形成薄的氮化物层，并且通过氮化物层形成沟槽并进入到半导体衬底中，然后填充。然后使用固定磨料CMP工艺将晶片平坦化，以减轻或避免浅沟槽隔离工艺中的台阶高度。然后在平坦化之后去除氮化物层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式