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1. 发明申请

US20080237640A1 N-FACE HIGH ELECTRON MOBILITY TRANSISTORS WITH LOW BUFFER LEAKAGE AND LOW PARASITIC RESISTANCE 有权
标题翻译：具有低缓冲层漏电和低抗隔离性的N面高电子移动晶体管
公开(公告)号：US20080237640A1
公开(公告)日：2008-10-02
申请号：US12059902
申请日：2008-03-31
申请人： Umesh K. Mishra , Yi Pei , Siddharth Rajan , Man Hoi Wong
发明人： Umesh K. Mishra , Yi Pei , Siddharth Rajan , Man Hoi Wong
IPC分类号： H01L29/267 , H01L21/205 , H01L21/336
CPC分类号： H01L29/7786 , H01L21/02378 , H01L21/02433 , H01L21/02458 , H01L21/02516 , H01L21/0254 , H01L29/0891 , H01L29/1608 , H01L29/2003
摘要： A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.
摘要翻译：一种用于制造具有低缓冲器泄漏的氮面（N面）氮化物基电子器件的方法，包括用AlGaInN成核层从衬底隔离缓冲器以抑制从衬底掺入缓冲器中的杂质。还公开了一种用于制造具有低寄生电阻和高击穿的N面氮化物基电子器件的方法，其包括用导电层封装器件结构以提供极低的访问和/或接触电阻。

2. 发明授权

US07935985B2 N-face high electron mobility transistors with low buffer leakage and low parasitic resistance 有权
标题翻译：具有低缓冲器泄漏和低寄生电阻的N面高电子迁移率晶体管
公开(公告)号：US07935985B2
公开(公告)日：2011-05-03
申请号：US12059902
申请日：2008-03-31
申请人： Umesh K. Mishra , Yi Pei , Siddharth Rajan , Man Hoi Wong
发明人： Umesh K. Mishra , Yi Pei , Siddharth Rajan , Man Hoi Wong
IPC分类号： H01L29/66
CPC分类号： H01L29/7786 , H01L21/02378 , H01L21/02433 , H01L21/02458 , H01L21/02516 , H01L21/0254 , H01L29/0891 , H01L29/1608 , H01L29/2003
摘要： A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.
摘要翻译：一种用于制造具有低缓冲器泄漏的氮面（N面）氮化物基电子器件的方法，包括用AlGaInN成核层从衬底隔离缓冲器以抑制从衬底掺入缓冲器中的杂质。还公开了一种用于制造具有低寄生电阻和高击穿的N面氮化物基电子器件的方法，其包括用导电层封装器件结构以提供极低的访问和/或接触电阻。

3. 发明授权

US07525130B2 Polarization-doped field effect transistors (POLFETS) and materials and methods for making the same 有权
标题翻译：极化掺杂场效应晶体管（POLFETS）及其制作方法
公开(公告)号：US07525130B2
公开(公告)日：2009-04-28
申请号：US11241804
申请日：2005-09-29
申请人： Umesh K. Mishra , Huili Xing , Debdeep Jena , Siddharth Rajan
发明人： Umesh K. Mishra , Huili Xing , Debdeep Jena , Siddharth Rajan
IPC分类号： H01L31/00
CPC分类号： H01L29/812 , H01L29/1029 , H01L29/2003 , H01L29/7783 , H01L29/7787
摘要： Novel GaN/AlGaN metal-semiconductor field-effect transistor (MESFET) structures grown without any impurity doping in the channel. A high-mobility polarization-induced bulk channel charge is created by grading the channel region linearly from GaN to Al0.3Ga0.7N over a distance, e.g., 1000 Å. A polarization-doped field effect transistor (PolFET) was fabricated and tested under DC and RF conditions. A current density of 850 mA/mm and transconductance of 93 mS/mm was observed under DC conditions. Small-signal characterization of 0.7 μm gate length devices had a cutoff frequency, fτ=19 GHz, and a maximum oscillation of fmax=46 GHz. The PolFETs perform better than comparable MESFETs with impurity-doped channels, and are suitable for high microwave power applications. An important advantage of these devices over AlGaN/GaN HEMTs is that the transconductance vs. gate voltage profile can be tailored by compositional grading for better large-signal linearity.
摘要翻译：新型GaN / AlGaN金属半导体场效应晶体管（MESFET）结构在通道中没有任何杂质掺杂生长。通过在一定距离（例如）1000处将通道区域从GaN线性地分级至Al 0.3 Ga 0.7 N来产生高迁移率极化诱导的体沟道电荷。在DC和RF条件下制造和测试偏振掺杂场效应晶体管（PolFET）。在直流条件下观察到电流密度为850mA / mm，跨导为93mS / mm。 0.7mm门极长度器件的小信号表征具有截止频率ftau = 19GHz，fmax = 46GHz的最大振荡。 PolFET比具有杂质掺杂通道的可比MESFET性能更好，适用于高微波功率应用。这些器件对AlGaN / GaN HEMT的一个重要优点是跨导与栅极电压分布可以通过组合分级来定制，以获得更好的大信号线性度。

4. 发明申请

US20100264461A1 N-polar aluminum gallium nitride/gallium nitride enhancement-mode field effect transistor 有权
标题翻译：氮化镓氮化镓/氮化镓增强型场效应晶体管
公开(公告)号：US20100264461A1
公开(公告)日：2010-10-21
申请号：US11523286
申请日：2006-09-18
申请人： Siddharth Rajan , Chang Soo Suh , James S. Speck , Umesh K. Mishra
发明人： Siddharth Rajan , Chang Soo Suh , James S. Speck , Umesh K. Mishra
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/045 , H01L29/2003 , H01L29/432 , H01L29/7781 , H01L29/7783 , H01L29/7784
摘要： A novel enhancement mode field effect transistor (FET), such as a High Electron Mobility Transistors (HEMT), has an N-polar surface uses polarization fields to reduce the electron population under the gate in the N-polar orientation, has improved dispersion suppression, and low gate leakage.
摘要翻译：一种新型的增强型场效应晶体管（FET），例如高电子迁移率晶体管（HEMT），具有N-极性表面，利用极化场来减小N极方向栅极下的电子群，改善了色散抑制，低栅极泄漏。

5. 发明授权

US07948011B2 N-polar aluminum gallium nitride/gallium nitride enhancement-mode field effect transistor 有权
标题翻译：氮化镓氮化镓/氮化镓增强型场效应晶体管
公开(公告)号：US07948011B2
公开(公告)日：2011-05-24
申请号：US11523286
申请日：2006-09-18
申请人： Siddharth Rajan , Chang Soo Suh , James S. Speck , Umesh K. Mishra
发明人： Siddharth Rajan , Chang Soo Suh , James S. Speck , Umesh K. Mishra
IPC分类号： H01L29/66
CPC分类号： H01L29/045 , H01L29/2003 , H01L29/432 , H01L29/7781 , H01L29/7783 , H01L29/7784
摘要： A novel enhancement mode field effect transistor (FET), such as a High Electron Mobility Transistors (HEMT), has an N-polar surface uses polarization fields to reduce the electron population under the gate in the N-polar orientation, has improved dispersion suppression, and low gate leakage.
摘要翻译：一种新型的增强型场效应晶体管（FET），例如高电子迁移率晶体管（HEMT），具有N-极性表面，利用极化场来减小N极方向栅极下的电子群，改善色散抑制，低栅极泄漏。

6. 发明申请

US20090085065A1 METHOD TO FABRICATE III-N SEMICONDUCTOR DEVICES ON THE N-FACE OF LAYERS WHICH ARE GROWN IN THE III-FACE DIRECTION USING WAFER BONDING AND SUBSTRATE REMOVAL 审中-公开
标题翻译：使用波形焊接和基板去除在III面形成的层的N面上制造III-N半导体器件的方法
公开(公告)号：US20090085065A1
公开(公告)日：2009-04-02
申请号：US12059907
申请日：2008-03-31
申请人： Umesh K. Mishra , Lee S. McCarthy , Chang Soo Suh , Siddharth Rajan
发明人： Umesh K. Mishra , Lee S. McCarthy , Chang Soo Suh , Siddharth Rajan
IPC分类号： H01L29/778 , H01L21/18 , H01L21/20
CPC分类号： H01L29/66462 , H01L21/187 , H01L29/045 , H01L29/2003 , H01L29/7783
摘要： A method for fabricating III-N semiconductor devices on the N-face of layers comprising (a) growing a III-nitride semiconductor device structure in a Ga-polar direction on a substrate, (b) attaching a Ga face of the III-nitride semiconductor device structure to a host substrate, and (c) removing the substrate to expose the N-face surface of the III-nitride semiconductor device structure. An N-polar (000-1) oriented III-nitride semiconductor device is also disclosed, comprising one or more (000-1) oriented nitride layers, each having an N-face opposite a group III-face, wherein at least one N-face is an at least partially exposed N-face, and a host substrate attached to one of the group III-faces.
摘要翻译：一种用于在层的N面上制造III-N半导体器件的方法，包括（a）在衬底上生长Ga极性方向上的III族氮化物半导体器件结构，（b）将III族氮化物的Ga面半导体器件结构，以及（c）去除衬底以露出III族氮化物半导体器件结构的N面。还公开了一种N极（000-1）取向的III族氮化物半导体器件，其包括一个或多个（000-1）取向的氮化物层，每个具有与III族面相反的N面，其中至少一个N 表面是至少部分暴露的N面，以及附着到III组面中的一个的主体衬底。

7. 发明授权

US08159002B2 Heterostructure device and associated method 有权
标题翻译：异质结构装置及相关方法
公开(公告)号：US08159002B2
公开(公告)日：2012-04-17
申请号：US11961532
申请日：2007-12-20
申请人： Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
发明人： Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/207
摘要： A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.
摘要翻译：异质结构器件包括具有第一区域，第二区域和第三区域的半导体多层结构。第一区域耦合到源电极，第二区域耦合到漏电极。第三区域设置在第一区域和第二区域之间。第三区域提供从源电极到漏电极的可切换导电路径。第三区域包括碘离子。一种系统包括包括该器件的异质结构场效应晶体管。

8. 发明申请

US20090159929A1 HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD 有权
标题翻译：异体结构设备及相关方法
公开(公告)号：US20090159929A1
公开(公告)日：2009-06-25
申请号：US11961532
申请日：2007-12-20
申请人： Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
发明人： Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/207
摘要： A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.
摘要翻译：异质结构器件包括具有第一区域，第二区域和第三区域的半导体多层结构。第一区域耦合到源电极，第二区域耦合到漏电极。第三区域设置在第一区域和第二区域之间。第三区域提供从源电极到漏电极的可切换导电路径。第三区域包括碘离子。一种系统包括包括该器件的异质结构场效应晶体管。

9. 发明授权

US08697506B2 Heterostructure device and associated method 有权
标题翻译：异质结构装置及相关方法
公开(公告)号：US08697506B2
公开(公告)日：2014-04-15
申请号：US13418566
申请日：2012-03-13
申请人： Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
发明人： Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
IPC分类号： H01L21/335
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/207
摘要： A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.
摘要翻译：提供了一种制造异质结构器件的方法，其包括将离子注入到多层结构的表面的一部分中。碘离子注入第一区域和第二区域之间以形成第三区域。电荷从第三区域中的二维电子气（2DEG）通道中消耗，以形成从第一区域到第二区域的可逆的非导电通路。在向靠近第三区域的栅电极施加电压电位时，允许电流从第一区域流到第二区域。

10. 发明授权

US09478699B2 Nanoscale emitters with polarization grading 有权
标题翻译：具有极化分级的纳米级发射体
公开(公告)号：US09478699B2
公开(公告)日：2016-10-25
申请号：US13819006
申请日：2011-08-25
申请人： Roberto C. Myers , Siddharth Rajan
发明人： Roberto C. Myers , Siddharth Rajan
IPC分类号： H01L33/04 , B82Y10/00 , B82Y30/00 , H01L21/02 , H01L29/06 , H01L29/12 , H01L29/15 , H01L29/205 , H01L29/66 , H01L29/775 , H01L29/861 , H01L31/0352 , H01L31/065 , H01L31/109 , H01L31/18 , H01L33/18 , H01L29/20 , H01L33/08 , H01L33/32 , B82Y20/00
CPC分类号： H01L33/04 , B82Y10/00 , B82Y20/00 , B82Y30/00 , H01L21/02458 , H01L21/0251 , H01L21/0254 , H01L21/02573 , H01L21/02603 , H01L21/02636 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/122 , H01L29/15 , H01L29/2003 , H01L29/205 , H01L29/66469 , H01L29/775 , H01L29/861 , H01L31/035227 , H01L31/03529 , H01L31/065 , H01L31/109 , H01L31/1848 , H01L31/1852 , H01L33/08 , H01L33/18 , H01L33/32 , H01L2924/0002 , Y02E10/544 , H01L2924/00
摘要： A nanowire comprises a polar semiconductor material that is compositionally graded along the nanowire from a first end to a second end to define a polarization doping profile along the nanowire from the first end to the second end. The polar semiconductor material may comprise a group IH-nitride semiconductor, such as an alloy of GaN and AlN, or an alloy of GaN and InN. Such nanowires may be formed by nucleating the first ends on a substrate, growing the nanowires by depositing polar semiconductor material on the nucleated first ends on a selected growth face, and compositionally grading the nanowires during growth to impart the polarization doping. The direction of the compositional grading may be reversed during the growing of the nanowires to reverse the type of the imparted polarization doping. In some embodiments, the reversing forms n/p or p/n junctions in the nanowires.
摘要翻译：纳米线包括从第一端到第二端在纳米线上组成分级的极性半导体材料，以限定沿着纳米线从第一端到第二端的偏振掺杂分布。极性半导体材料可以包括诸如GaN和AlN的合金或GaN和InN的合金的III族氮化物半导体。这样的纳米线可以通过在基底上成核第一端而形成，通过在选择的生长面上的有核的第一端上沉积极性半导体材料来生长纳米线，并且在生长期间组合地对纳米线进行分级以赋予偏振掺杂。在纳米线的生长期间，组成分级的方向可以相反，以反转所赋予的偏振掺杂的类型。在一些实施方案中，反转在纳米线中形成n / p或p / n结。

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