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1. 发明授权

US08039352B2 Polarization-induced barriers for N-face nitride-based electronics 失效
标题翻译：用于N面氮化物基电子器件的极化诱导屏障
公开(公告)号：US08039352B2
公开(公告)日：2011-10-18
申请号：US12127661
申请日：2008-05-27
申请人： Umesh K. Mishra , Tomas A. Palacios Gutierrez , Man-Hoi Wong
发明人： Umesh K. Mishra , Tomas A. Palacios Gutierrez , Man-Hoi Wong
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/338
CPC分类号： H01L29/7783 , H01L29/2003 , H01L29/66462 , H01L29/7787
摘要： A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III-nitride layer, to shift, e.g., raise or lower, the first III-nitride layer's energy band with respect to the second III-nitride layer's energy band by a pre-determined amount. The first III-nitride layer and second III-nitride layer each have a higher or lower polarization coefficient than the III-nitride interlayer's polarization coefficient.
摘要翻译：一种用于制造氮 - 面（N面）氮化物基电子器件的势垒的方法，包括使用位于第一III族氮化物层和第二层氮化物层之间的III族氮化物中间层的厚度和极化感应电场 III族氮化物层相对于第二III族氮化物层的能带移动（例如）升高或降低第一III族氮化物层的能带预定量。第一III族氮化物层和第二III族氮化物层各自具有比III族氮化物夹层的极化系数更高或更低的偏振系数。

2. 发明申请

US20090218599A1 POLARIZATION-INDUCED BARRIERS FOR N-FACE NITRIDE-BASED ELECTRONICS 失效
标题翻译：用于基于N面的氮化物电极的极化诱导障碍
公开(公告)号：US20090218599A1
公开(公告)日：2009-09-03
申请号：US12127661
申请日：2008-05-27
申请人： Umesh K. Mishra , Tomas A. Palacios Gutierrez , Man Hoi Wong
发明人： Umesh K. Mishra , Tomas A. Palacios Gutierrez , Man Hoi Wong
IPC分类号： H01L29/778
CPC分类号： H01L29/7783 , H01L29/2003 , H01L29/66462 , H01L29/7787
摘要： A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III-nitride layer, to shift, e.g., raise or lower, the first III-nitride layer's energy band with respect to the second III-nitride layer's energy band by a pre-determined amount. The first III-nitride layer and second III-nitride layer each have a higher or lower polarization coefficient than the III-nitride interlayer's polarization coefficient.
摘要翻译：一种用于制造氮 - 面（N面）氮化物基电子器件的势垒的方法，包括使用位于第一III族氮化物层和第二层氮化物层之间的III族氮化物中间层的厚度和极化感应电场 III族氮化物层相对于第二III族氮化物层的能带移动（例如）升高或降低第一III族氮化物层的能带预定量。第一III族氮化物层和第二III族氮化物层各自具有比III族氮化物夹层的极化系数更高或更低的偏振系数。

3. 发明授权

US07935985B2 N-face high electron mobility transistors with low buffer leakage and low parasitic resistance 有权
标题翻译：具有低缓冲器泄漏和低寄生电阻的N面高电子迁移率晶体管
公开(公告)号：US07935985B2
公开(公告)日：2011-05-03
申请号：US12059902
申请日：2008-03-31
申请人： Umesh K. Mishra , Yi Pei , Siddharth Rajan , Man Hoi Wong
发明人： Umesh K. Mishra , Yi Pei , Siddharth Rajan , Man Hoi Wong
IPC分类号： H01L29/66
CPC分类号： H01L29/7786 , H01L21/02378 , H01L21/02433 , H01L21/02458 , H01L21/02516 , H01L21/0254 , H01L29/0891 , H01L29/1608 , H01L29/2003
摘要： A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.
摘要翻译：一种用于制造具有低缓冲器泄漏的氮面（N面）氮化物基电子器件的方法，包括用AlGaInN成核层从衬底隔离缓冲器以抑制从衬底掺入缓冲器中的杂质。还公开了一种用于制造具有低寄生电阻和高击穿的N面氮化物基电子器件的方法，其包括用导电层封装器件结构以提供极低的访问和/或接触电阻。

4. 发明申请

US20080237640A1 N-FACE HIGH ELECTRON MOBILITY TRANSISTORS WITH LOW BUFFER LEAKAGE AND LOW PARASITIC RESISTANCE 有权
标题翻译：具有低缓冲层漏电和低抗隔离性的N面高电子移动晶体管
公开(公告)号：US20080237640A1
公开(公告)日：2008-10-02
申请号：US12059902
申请日：2008-03-31
申请人： Umesh K. Mishra , Yi Pei , Siddharth Rajan , Man Hoi Wong
发明人： Umesh K. Mishra , Yi Pei , Siddharth Rajan , Man Hoi Wong
IPC分类号： H01L29/267 , H01L21/205 , H01L21/336
CPC分类号： H01L29/7786 , H01L21/02378 , H01L21/02433 , H01L21/02458 , H01L21/02516 , H01L21/0254 , H01L29/0891 , H01L29/1608 , H01L29/2003
摘要： A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.
摘要翻译：一种用于制造具有低缓冲器泄漏的氮面（N面）氮化物基电子器件的方法，包括用AlGaInN成核层从衬底隔离缓冲器以抑制从衬底掺入缓冲器中的杂质。还公开了一种用于制造具有低寄生电阻和高击穿的N面氮化物基电子器件的方法，其包括用导电层封装器件结构以提供极低的访问和/或接触电阻。

5. 发明授权

US09496353B2 Fabrication of single or multiple gate field plates 有权
标题翻译：制造单栅极或多栅极场板
公开(公告)号：US09496353B2
公开(公告)日：2016-11-15
申请号：US12898341
申请日：2010-10-05
申请人： Alessandro Chini , Umesh K. Mishra , Primit Parikh , Yifeng Wu
发明人： Alessandro Chini , Umesh K. Mishra , Primit Parikh , Yifeng Wu
IPC分类号： H01L29/40 , H01L27/06 , H01L29/423 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/207 , H01L29/417 , H01L29/78
CPC分类号： H01L29/404 , H01L27/0605 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/401 , H01L29/402 , H01L29/41766 , H01L29/42312 , H01L29/42316 , H01L29/66462 , H01L29/7787 , H01L29/785
摘要： A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
摘要翻译：使用在场效应晶体管的表面上的介电材料沉积/生长，介电材料蚀刻和金属蒸发的连续步骤来制造单栅极或多栅极场板的工艺。这种制造工艺允许对场板操作的严格控制，因为介电材料沉积/生长通常是良好可控的工艺。此外，沉积在器件表面上的电介质材料不需要从器件本征区域去除：这基本上使得能够实现电镀设备，而不需要低损耗介电材料干/湿蚀刻。使用多个栅极场板还通过多个连接降低栅极电阻，从而提高大的周边和/或亚微米栅极器件的性能。

6. 发明授权

US09129977B2 Method of controlling stress in group-III nitride films deposited on substrates 有权
标题翻译：控制沉积在衬底上的III族氮化物膜的应力的方法
公开(公告)号：US09129977B2
公开(公告)日：2015-09-08
申请号：US13306763
申请日：2011-11-29
申请人： Hugues Marchand , Brendan J. Moran , Umesh K. Mishra , James S. Speck
发明人： Hugues Marchand , Brendan J. Moran , Umesh K. Mishra , James S. Speck
IPC分类号： H01L33/32 , H01L29/267 , H01L23/00 , C30B25/02 , C30B29/40 , H01L21/02 , H01L33/00 , H01L29/20 , H01L29/205 , H01L33/12
CPC分类号： H01L23/562 , C30B25/02 , C30B29/403 , C30B29/406 , H01L21/02378 , H01L21/02381 , H01L21/02458 , H01L21/0251 , H01L21/0254 , H01L21/0262 , H01L29/2003 , H01L29/205 , H01L33/0025 , H01L33/0066 , H01L33/0075 , H01L33/12 , H01L33/32 , H01L2924/0002 , H01L2924/00
摘要： Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
摘要翻译：公开了控制沉积在硅和碳化硅衬底上的GaN膜中的应力控制方法和由其制备的膜。典型的方法包括提供衬底并在衬底上沉积梯度的氮化镓层，其具有基本上连续等级的从初始组成到由生长室中的至少一种前体的供应形成的最终组成的变化的组成，而不会中断在供应。典型的半导体膜包括沉积在衬底上的衬底和梯度的氮化镓层，其具有从初始组成到最终组成的基本连续等级的变化的组成，其由在生长室中供应至少一种前体而形成，而不会中断在供应。

7. 发明授权

US08324637B2 High efficiency LEDs with tunnel junctions 有权
标题翻译：具有隧道结的高效率LED
公开(公告)号：US08324637B2
公开(公告)日：2012-12-04
申请号：US12782107
申请日：2010-05-18
申请人： James P. Ibbetson , Bernd P. Keller , Umesh K. Mishra
发明人： James P. Ibbetson , Bernd P. Keller , Umesh K. Mishra
IPC分类号： H01L27/15
CPC分类号： H01L33/04 , H01L33/0016 , H01L33/08 , H01L33/32
摘要： An LED made from a wide band gap semiconductor material and having a low resistance p-type confinement layer with a tunnel junction in a wide band gap semiconductor device is disclosed. A dissimilar material is placed at the tunnel junction where the material generates a natural dipole. This natural dipole is used to form a junction having a tunnel width that is smaller than such a width would be without the dissimilar material. A low resistance p-type confinement layer having a tunnel junction in a wide band gap semiconductor device may be fabricated by generating a polarization charge in the junction of the confinement layer, and forming a tunnel width in the junction that is smaller than the width would be without the polarization charge. Tunneling through the tunnel junction in the confinement layer may be enhanced by the addition of impurities within the junction. These impurities may form band gap states in the junction.
摘要翻译：公开了一种由宽带隙半导体材料制成的LED，并具有在宽带隙半导体器件中具有隧道结的低电阻p型约束层。不同的材料放置在材料产生天然偶极子的隧道结处。该天然偶极子用于形成隧道宽度小于不具有不同材料的宽度的接合点。在宽带隙半导体器件中具有隧道结的低电阻p型限制层可以通过在限制层的接合处产生极化电荷并在接合部中形成小于宽度的隧道宽度来制造没有极化电荷。可以通过在连接处添加杂质来增强通过限制层中的隧道结的隧穿。这些杂质可能在结中形成带隙状态。

8. 发明授权

US08193020B2 Method for heteroepitaxial growth of high-quality N-face GaN, InN, and AlN and their alloys by metal organic chemical vapor deposition 有权
标题翻译：高品质N面GaN，InN和AlN及其合金的金属有机化学气相沉积异质外延生长方法
公开(公告)号：US08193020B2
公开(公告)日：2012-06-05
申请号：US12466705
申请日：2009-05-15
申请人： Stacia Keller , Umesh K. Mishra , Nicholas K. Fichtenbaum
发明人： Stacia Keller , Umesh K. Mishra , Nicholas K. Fichtenbaum
IPC分类号： H01L21/20
CPC分类号： C30B25/02 , C30B29/403 , H01L21/02378 , H01L21/02381 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/02538 , H01L21/0254 , H01L21/02573 , H01L21/0262
摘要： Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (μm sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible.
摘要翻译：公开了通过MOCVD生长的N面GaN薄膜的平滑，高质量薄膜异质外延生长的方法。使用错误取向的衬底并且可能使衬底氮化使得能够生长平滑的N面GaN和其他III族氮化物膜，如本文所公开的。本发明还避免了典型的大（μm尺寸）六边形特征，这使得N面GaN材料不适合于器件应用。本发明允许平滑，高质量的膜的生长，这使得N面装置的发展成为可能。

9. 发明授权

US08188458B2 Non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices 有权
标题翻译：非极性（Al，B，In，Ga）N量子阱和异质结构材料和器件
公开(公告)号：US08188458B2
公开(公告)日：2012-05-29
申请号：US13099834
申请日：2011-05-03
申请人： Michael D. Craven , Stacia Keller , Steven P. DenBaars , Tal Margalith , James S. Speck , Shuji Nakamura , Umesh K. Mishra
发明人： Michael D. Craven , Stacia Keller , Steven P. DenBaars , Tal Margalith , James S. Speck , Shuji Nakamura , Umesh K. Mishra
IPC分类号： H01L29/15
CPC分类号： C30B29/403 , C30B25/02 , C30B25/04 , C30B25/105 , C30B25/18 , C30B29/406 , C30B29/605 , H01L21/0237 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02609 , H01L21/0262 , H01L21/02639 , H01L21/02647
摘要： A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 20) a-plane GaN layers are grown on an r-plane (1 102) sapphire substrate using MOCVD. These non-polar (11 20) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.
摘要翻译：一种形成非极性（Al，B，In，Ga）N量子阱和异质结构材料和器件的方法。使用MOCVD在非平面（1120）蓝宝石衬底上生长非极性（11 20）a面GaN层。这些非极性（11 20）a面GaN层包括用于产生非极性（Al，B，In，Ga）N量子阱和异质结构材料和器件的模板。

10. 发明授权

US08114717B2 Methods to shape the electric field in electron devices, passivate dislocations and point defects, and enhance the luminescence efficiency of optical devices 有权
标题翻译：在电子器件中形成电场的方法，钝化位错和点缺陷，提高光器件的发光效率
公开(公告)号：US08114717B2
公开(公告)日：2012-02-14
申请号：US11599874
申请日：2006-11-15
申请人： Tomas Palacios , Likun Shen , Umesh K. Mishra
发明人： Tomas Palacios , Likun Shen , Umesh K. Mishra
IPC分类号： H01L21/335
CPC分类号： H01L29/2003 , H01L29/207 , H01L29/402 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L33/0095
摘要： A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage. Three different methods to introduce dispersion in the 50 nm closest to the gate are described: (1) introduction of a small gap between the passivation and the gate metal, (2) gradually reducing the thickness of the passivation, and (3) gradually reducing the thickness of the AlGaN cap layer in the region close the gate.
摘要翻译：公开了可以在1,2或3维度的电子设备中形成电场分布的氟处理。还公开了通过将受控量的分散引入到器件中来增加AlGaN / GaN高电子迁移率晶体管的击穿电压的方法。该色散足够大以减少通道中的峰值电场，但是足够低以便不会导致器件的输出功率的显着降低。在该设计中，整个晶体管被钝化以抵消色散，除了在栅极的漏极侧旁边的50至100nm宽的小区域之外。在该区域中，表面捕集器产生有限的色散，这将扩散栅极边缘处的高电场，从而增加击穿电压。描述了在最接近栅极的50nm中引入色散的三种不同的方法：（1）在钝化和栅极金属之间引入小的间隙，（2）逐渐减小钝化的厚度，和（3）逐渐降低在关闭栅极的区域中的AlGaN覆盖层的厚度。

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