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1. 发明授权

US07745270B2 Tri-gate patterning using dual layer gate stack 有权
标题翻译：使用双层栅极堆叠的三栅极图案化
公开(公告)号：US07745270B2
公开(公告)日：2010-06-29
申请号：US12006047
申请日：2007-12-28
申请人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
发明人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L21/84
CPC分类号： H01L21/823821 , H01L29/66795 , H01L29/785
摘要： In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A polysilicon layer is formed over the silicon germanium layer and is polished. The polysilicon layer over the first work function metal layer is thicker than the polysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the polysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.
摘要翻译：通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。在衬底上形成高介电常数层。在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。在第一和第二功函数金属层上形成硅锗层。在硅锗层上形成多晶硅层并进行抛光。第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。硬掩模被图案化并用于蚀刻多晶硅层和硅锗层以产生栅极堆叠。硅锗层的蚀刻速率比第一功函数金属层更快。

2. 发明申请

US20070287255A1 Protection of three dimensional transistor structures during gate stack etch 有权
标题翻译：在栅堆叠蚀刻期间保护三维晶体管结构
公开(公告)号：US20070287255A1
公开(公告)日：2007-12-13
申请号：US11452883
申请日：2006-06-13
申请人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
发明人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.
摘要翻译：本发明的实施例包括与具有高k电介质的三维晶体管和金属栅极相关的装置和方法，其翅片由其顶表面上的硬掩模层保护。在一个实施例中，硬掩模层包括氧化物。

3. 发明申请

US20090170267A1 Tri-gate patterning using dual layer gate stack 有权
标题翻译：使用双层栅极堆叠的三栅极图案化
公开(公告)号：US20090170267A1
公开(公告)日：2009-07-02
申请号：US12006047
申请日：2007-12-28
申请人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
发明人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L21/336
CPC分类号： H01L21/823821 , H01L29/66795 , H01L29/785
摘要： In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A ploysilicon layer is formed over the silicon germanium layer and is polished. The ploysilicon layer over the first work function metal layer is thicker than the ploysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the ploysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.
摘要翻译：通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。在衬底上形成高介电常数层。在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。在第一和第二功函数金属层上形成硅锗层。在硅锗层上方形成硅层，并进行抛光。第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。硬掩模被图案化并用于蚀刻合金层和硅锗层以产生栅极堆叠。硅锗层的蚀刻速率比第一功函数金属层更快。

4. 发明授权

US07521775B2 Protection of three dimensional transistor structures during gate stack etch 有权
标题翻译：在栅堆叠蚀刻期间保护三维晶体管结构
公开(公告)号：US07521775B2
公开(公告)日：2009-04-21
申请号：US11452883
申请日：2006-06-13
申请人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
发明人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
IPC分类号： H01L29/06
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.
摘要翻译：本发明的实施例包括与具有高k电介质的三维晶体管和金属栅极相关的装置和方法，其翅片由其顶表面上的硬掩模层保护。在一个实施例中，硬掩模层包括氧化物。

5. 发明申请

US20140054548A1 TECHNIQUES FOR FORMING NON-PLANAR GERMANIUM QUANTUM WELL DEVICES 审中-公开
公开(公告)号：US20140054548A1
公开(公告)日：2014-02-27
申请号：US14069880
申请日：2013-11-01
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been-Yih Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been-Yih Jin , Robert S. Chau
IPC分类号： H01L29/775 , H01L21/76 , H01L29/66
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

6. 发明申请

US20090057846A1 METHOD TO FABRICATE ADJACENT SILICON FINS OF DIFFERING HEIGHTS 审中-公开
标题翻译：用于织造不同高度的相似硅纤维的方法
公开(公告)号：US20090057846A1
公开(公告)日：2009-03-05
申请号：US11848235
申请日：2007-08-30
申请人： Brian S. Doyle , Been-Yih Jin , Uday Shah
发明人： Brian S. Doyle , Been-Yih Jin , Uday Shah
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L29/785 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L29/66795
摘要： A method to fabricate adjacent silicon fins of differing heights comprises providing a silicon substrate having an isolation layer deposited thereon, patterning the isolation layer to form first and second isolation structures, patterning the silicon substrate to form a first silicon fin beneath the first isolation structure and a second silicon fin beneath the second isolation structure, depositing an insulating layer on the substrate, planarizing the insulating layer to expose top surfaces of the first and second isolation structures, depositing and patterning a masking layer to mask the first isolation structure but not the second isolation structure, applying a wet etch to remove the second isolation structure and expose the second silicon fin, epitaxially depositing a silicon layer on the second silicon fin, and recessing the insulating layer to expose at least a portion of the first silicon fin and at least a portion of the second silicon fin.
摘要翻译：制造不同高度的相邻硅散热片的方法包括提供具有沉积在其上的隔离层的硅衬底，图案化隔离层以形成第一和第二隔离结构，图案化硅衬底以在第一隔离结构下方形成第一硅片，在所述第二隔离结构下方的第二硅鳍片，在所述衬底上沉积绝缘层，平坦化所述绝缘层以暴露所述第一和第二隔离结构的顶表面，沉积和图案化掩模层以掩蔽所述第一隔离结构而不是所述第二隔离结构隔离结构，施加湿蚀刻以去除所述第二隔离结构并暴露所述第二硅鳍，在所述第二硅鳍上外延沉积硅层，以及使所述绝缘层凹陷以暴露所述第一硅片的至少一部分，并且至少第二硅片的一部分。

7. 发明授权

US07763943B2 Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin 有权
标题翻译：通过结合部分金属翅片来减少多栅极器件的外部电阻
公开(公告)号：US07763943B2
公开(公告)日：2010-07-27
申请号：US11964623
申请日：2007-12-26
申请人： Ravi Pillarisetty , Uday Shah , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
发明人： Ravi Pillarisetty , Uday Shah , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/785 , H01L29/66795
摘要： Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.
摘要翻译：通常描述通过结合部分金属翅片来降低多栅极器件的外部电阻。在一个示例中，设备包括半导体衬底和与半导体衬底耦合的多栅极晶体管器件的一个或多个鳍片，该一个或多个鳍片具有栅极区域，源极区域和漏极区域，栅极区域设置在源极和漏极区域之间，其中一个或多个鳍片的栅极区域包括半导体材料，并且其中一个或多个鳍片的源极和漏极区域包括金属部分和半导体部分，金属部分和半导体部分联接在一起。

8. 发明申请

US20090039476A1 Apparatus and method for selectively recessing spacers on multi-gate devices 审中-公开
标题翻译：用于在多栅极器件上选择性地凹入间隔物的装置和方法
公开(公告)号：US20090039476A1
公开(公告)日：2009-02-12
申请号：US12287319
申请日：2008-10-07
申请人： Jack T. Kavalieros , Uday Shah , Willy Rachmady , Brian S. Doyle
发明人： Jack T. Kavalieros , Uday Shah , Willy Rachmady , Brian S. Doyle
IPC分类号： H01L21/311 , H01L21/306 , H01L29/51
CPC分类号： H01L29/4983 , H01L29/66628 , H01L29/66795 , H01L29/785 , Y10S257/90
摘要： Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述用于在多栅极晶体管的一部分上制造间隔物而不在多栅极晶体管的另一部分上形成间隔物的方法的实施例。可以描述和要求保护其他实施例。

9. 发明授权

US08030163B2 Reducing external resistance of a multi-gate device using spacer processing techniques 有权
标题翻译：使用间隔物处理技术降低多栅极器件的外部电阻
公开(公告)号：US08030163B2
公开(公告)日：2011-10-04
申请号：US11964593
申请日：2007-12-26
申请人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
发明人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/785
摘要： A method includes depositing a sacrificial gate electrode to one or more multi-gate fins. The sacrificial gate electrode is patterned such that it is coupled to a gate region and substantially no sacrificial gate electrode is coupled to source and drain regions. A dielectric film is formed that is coupled to the source and drain regions. The sacrificial gate electrode is removed and a spacer gate dielectric is deposited to the gate region wherein substantially no spacer gate dielectric is deposited to the source and drain regions. The spacer gate dielectric is etched to completely remove the spacer gate dielectric from the gate region area that is to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric that is to be coupled with the final gate electrode that remains coupled with the dielectric film.
摘要翻译：一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上。牺牲栅电极被图案化，使得它被耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到源极和漏极区域。形成了与源极和漏极区域耦合的电介质膜。牺牲栅极电极被去除，并且间隔栅极电介质沉积到栅极区域，其中基本上没有间隔栅极电介质沉积到源区和漏极区。蚀刻间隔栅极电介质以完全去除要与最终栅电极耦合的栅极区域的间隔栅极电介质，除了与最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外，保持与电介质膜耦合。

10. 发明申请

US20090004868A1 Amorphous silicon oxidation patterning 审中-公开
标题翻译：非晶硅氧化图案化
公开(公告)号：US20090004868A1
公开(公告)日：2009-01-01
申请号：US11824489
申请日：2007-06-29
申请人： Brian S. Doyle , Uday Shah , Jack T. Kavalieros
发明人： Brian S. Doyle , Uday Shah , Jack T. Kavalieros
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L27/10861 , H01L28/90
摘要： In one embodiment, a method comprises forming a sacrificial amorphous silicon layer on a semiconductor substrate, forming a hardmask on the amorphous silicon layer, etching one or more lines in the sacrificial amorphous silicon layer, growing oxide structures on the amorphous silicon layer, and forming a trench in the semiconductor substrate between the oxide structures.
摘要翻译：在一个实施例中，一种方法包括在半导体衬底上形成牺牲非晶硅层，在非晶硅层上形成硬掩模，蚀刻牺牲非晶硅层中的一条或多条线，在非晶硅层上生长氧化物结构，以及形成氧化物结构之间的半导体衬底中的沟槽。

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