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    • 4. 发明授权
      US08030163B2 Reducing external resistance of a multi-gate device using spacer processing techniques 有权
    • Reducing external resistance of a multi-gate device using spacer processing techniques
    • 使用间隔物处理技术降低多栅极器件的外部电阻
    • US08030163B2
    • 2011-10-04
    • US11964593
    • 2007-12-26
    • Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
    • Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
    • H01L21/336
    • H01L29/66795 , H01L29/66545 , H01L29/785
    • A method includes depositing a sacrificial gate electrode to one or more multi-gate fins. The sacrificial gate electrode is patterned such that it is coupled to a gate region and substantially no sacrificial gate electrode is coupled to source and drain regions. A dielectric film is formed that is coupled to the source and drain regions. The sacrificial gate electrode is removed and a spacer gate dielectric is deposited to the gate region wherein substantially no spacer gate dielectric is deposited to the source and drain regions. The spacer gate dielectric is etched to completely remove the spacer gate dielectric from the gate region area that is to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric that is to be coupled with the final gate electrode that remains coupled with the dielectric film.
    • 一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上。 牺牲栅电极被图案化，使得它被耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到源极和漏极区域。 形成了与源极和漏极区域耦合的电介质膜。 牺牲栅极电极被去除，并且间隔栅极电介质沉积到栅极区域，其中基本上没有间隔栅极电介质沉积到源区和漏极区。 蚀刻间隔栅极电介质以完全去除要与最终栅电极耦合的栅极区域的间隔栅极电介质，除了与最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外， 保持与电介质膜耦合。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明申请
      US20090166741A1 REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES 有权
    • REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES
    • 使用间隔加工技术降低多门装置的外部电阻
    • US20090166741A1
    • 2009-07-02
    • US11964593
    • 2007-12-26
    • Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
    • Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
    • H01L29/94 , H01L21/336
    • H01L29/66795 , H01L29/66545 , H01L29/785
    • Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.
    • 通常描述使用间隔物处理技术降低多栅极器件的外部电阻。 在一个示例中，一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上，一个或多个多栅极鳍片包括栅极区域，源极区域和漏极区域，栅极区域设置在 源极和漏极区域，图案化牺牲栅极电极，使得牺牲栅电极材料耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到一个或多个多栅极鳍片的源极和漏极区域，形成电介质 薄膜耦合到一个或多个多栅极鳍片的源极和漏极区域，从一个或多个多栅极鳍片的栅极区域去除牺牲栅电极，将间隔栅极电介质沉积到该一个或多个多栅极散热片的栅极区域 多栅极翅片，其中基本上没有间隔栅极电介质沉积到一个或多个多栅极鳍片的源极和漏极区域，源极和漏极区域被电介质fi 并且蚀刻间隔栅极电介质，以将栅极区域的栅极区域完全去除以与最终栅电极耦合的间隔栅极电介质，除了要与保持耦合的最终栅电极耦合的间隔栅极电介质的剩余预定厚度 与电介质膜。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明申请
      US20110284965A1 REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES 审中-公开
    • REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES
    • 使用间隔加工技术降低多门装置的外部电阻
    • US20110284965A1
    • 2011-11-24
    • US13204987
    • 2011-08-08
    • Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
    • Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
    • H01L29/78
    • H01L29/66795 , H01L29/66545 , H01L29/785
    • Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more to multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.
    • 通常描述使用间隔物处理技术降低多栅极器件的外部电阻。 在一个示例中，一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上，一个或多个多栅极鳍片包括栅极区域，源极区域和漏极区域，栅极区域设置在 源极和漏极区域，图案化牺牲栅极电极，使得牺牲栅电极材料耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到一个或多个多栅极鳍片的源极和漏极区域，形成电介质 将一个或多个多栅极翅片的源极和漏极区域耦合到所述一个或多个多栅极散热片的栅极区域;将所述牺牲栅极电极从所述一个或多个至多个栅极鳍片的栅极区域移除;将间隔栅极电介质沉积到所述一个或多个栅极栅极栅极区域; 更多的多栅极鳍片，其中基本上没有间隔栅极电介质沉积到一个或多个多栅极鳍片的源极和漏极区域，源极和漏极区域被电介质保护 膜和蚀刻间隔栅极电介质以从栅极区域区域完全去除间隔栅极电介质，以与最终栅极电极耦合，除了与保持耦合的最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外 与电介质膜。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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