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1. 发明授权

US3824562A High speed random access memory shift register 失效
标题翻译：高速随机存取存储器移位寄存器
公开(公告)号：US3824562A
公开(公告)日：1974-07-16
申请号：US34653973
申请日：1973-03-30
申请人： US NAVY
发明人： LEIBOWITZ L , BATES C
IPC分类号： G06F5/10 , G11C19/00
CPC分类号： G06F5/10
摘要： A number of Random Access Memory (RAM) units are controlled by read-write logic, memory address counters, and a clock distribution function to provide a high speed shift register. The high speed capability is obtained through the use of a plurality of lower speed RAMs by sequentially processing input data from the first RAM to the second, then the third, etc. The output is taken from each RAM and fed to a latch so that while one RAM is providing data as an output, a subsequent RAM is able to manipulate and operate on subsequent data. Extremely long, high speed shift registers may be realized by this invention with particular interest in the area of signal processing of radar video returns.
摘要翻译：多个随机存取存储器（RAM）单元由读写逻辑，存储器地址计数器和时钟分配功能来控制，以提供高速移位寄存器。通过使用多个低速RAM，通过依次处理从第一RAM到第二RAM的输入数据，然后依次处理第三RAM等等，获得高速能力。输出取自每个RAM并被馈送到锁存器一个RAM提供数据作为输出，随后的RAM能够对后续数据进行操作和操作。非常长的高速移位寄存器可以通过本发明实现，特别关心在雷达视频返回的信号处理领域。

2. 发明授权

US3805031A Count and store synchronous binary counter 失效
标题翻译： COUNT和存储同步二进制计数器
公开(公告)号：US3805031A
公开(公告)日：1974-04-16
申请号：US29220372
申请日：1972-09-25
申请人： US NAVY
发明人： LEIBOWITZ L , BALDAUF R , STREET T
IPC分类号： H03K21/08 , H03K21/12 , H03K23/58
CPC分类号： H03K21/08 , H03K21/12 , H03K23/58
摘要： An improvement in a count and store binary counter system wherein the count is available immediately after the reception of the counting clock pulse. Thus, there is no need to wait for a successive ripple-through, and the possibility of erroneous outputs due to an intermediate ripple-through state is eliminated. The circuitry employed to accomplish the invention includesq among other things, a ripple-through binary counter coupled to an n-bit parallel register.
摘要翻译：计数和存储二进制计数器系统的改进，其中计数在接收计数时钟脉冲之后立即可用。因此，不需要等待连续的纹波，并且消除了由于中间纹波通过状态引起的错误输出的可能性。用于实现本发明的电路包括其中包括耦合到n位并行寄存器的纹波二进制计数器。

3. 发明授权

US3735271A Pulse width coded signal detector 失效
标题翻译：脉冲宽度信号检测器
公开(公告)号：US3735271A
公开(公告)日：1973-05-22
申请号：US3735271D
申请日：1971-10-22
申请人： US NAVY
发明人： LEIBOWITZ L
IPC分类号： G01R29/027 , H03K5/18
CPC分类号： G01R29/0273
摘要： Two one-shot circuits are triggered by an input data pulse to be interrogated. At the leading edge of the input pulse, one of the two one-shot circuits generates a pulse of the specified width minus the specified tolerance. The other one-shot circuit generates a pulse width equal to the specified tolerance at the trailing edge of the interrogated pulse. The output of the first one-shot circuit triggers a third one-shot circuit which in turn generates a pulse of a width equal to twice the specified tolerance. The outputs of the second and third one-shot circuits are combined in a NAND gate which generates the detection pulse to indicate that the interrogated pulse is within the specified tolerance. The detection pulse is generated as soon as the trailing edge of the interrogated pulse is received. Thus, two input data pulses can be placed as close together as possible as long as the individual pulse identity is maintained, making it possible to maximize the date rate. A multiplicty of detector circuits may be connected in a parallel manner, each generating a detection pulse upon the reception of a pulse specified length, thus permitting the decoding of an entire pulse-width-coded message.
摘要翻译：两个单触发电路由要询问的输入数据脉冲触发。在输入脉冲的前沿，两个单触发电路中的一个产生指定宽度的脉冲减去指定的公差。另一个单触发电路在询问脉冲的后沿产生等于指定公差的脉冲宽度。第一单触发电路的输出触发第三个单触发电路，该电路又产生一个宽度等于规定公差的两倍的脉冲。第二和第三单触发电路的输出组合在产生检测脉冲的“与非”门中，以指示询问脉冲在规定的公差内。一旦接收到询问脉冲的后沿，就产生检测脉冲。因此，只要维持单独的脉冲识别，就可以将两个输入数据脉冲尽可能靠近放置，使得可以使日期速率最大化。检测器电路的倍数可以以并行方式连接，每个检测器电路在接收到脉冲指定长度时产生检测脉冲，从而允许对整个脉冲宽度编码消息进行解码。

4. 发明授权

US3794994A Feedback integrator with pedestal elimination 失效
标题翻译：反馈整合器与消防措施
公开(公告)号：US3794994A
公开(公告)日：1974-02-26
申请号：US3794994D
申请日：1972-06-29
申请人： US NAVY
发明人： LEIBOWITZ L , BALDAUF R
IPC分类号： G01S7/292 , G06F17/10 , G06F17/18 , G01S9/06
CPC分类号： G06F17/18 , G01S7/2926 , G06F17/10
摘要： A digital feedback integrator, especially adapted to provide increased target detection ability in radar systems. The feedback integrator is employed in the signal processing circuitry and compensates for arithmetic truncation errors by advantageously avoiding a final truncation pedestal in the integrating output.
摘要翻译：数字反馈积分器，特别适用于在雷达系统中提供更高的目标检测能力。在信号处理电路中采用反馈积分器，并通过有利地避免积分输出中的最终截距基座来补偿算术截断误差。

5. 发明授权

US3765013A Self synchronous serial encoder/decoder 失效
标题翻译：自同步串行编码器/解码器
公开(公告)号：US3765013A
公开(公告)日：1973-10-09
申请号：US3765013D
申请日：1972-06-23
申请人： US NAVY
发明人： LEIBOWITZ L
IPC分类号： H03M9/00 , H04L25/45 , H03K13/24
CPC分类号： H03M9/00 , H04L25/45
摘要： A device to provide a simple means of translating a parallel nbit data word from a counter or the like to a serial format which is suitable for single channel recording or transmission over a single wire. Also, this device permits the decoding of serial data back to parallel form independent of the exact time location of the leading bit of the serial code.
摘要翻译：提供将并行n位数据字从计数器等转换成适用于单通道单通道记录或传输的串行格式的简单装置。而且，该设备允许将串行数据解码为独立于串行代码的前导位的精确时间位置的并行形式。

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