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1. 发明申请

US20080305605A1 METHOD FOR FORMING SURFACE STRAP 有权
标题翻译：形成表面带的方法
公开(公告)号：US20080305605A1
公开(公告)日：2008-12-11
申请号：US11940308
申请日：2007-11-14
申请人： Chih-Hao Cheng , Tzung-Han Lee , Chung-Yuan Lee
发明人： Chih-Hao Cheng , Tzung-Han Lee , Chung-Yuan Lee
IPC分类号： H01L21/20
CPC分类号： H01L27/10867
摘要： A method for forming a surface strap includes forming a deep trench capacitor having a conductive connection layer on its surface in the substrate and the conductive connection layer in contact with the conductive layer; forming a poly-Si layer covering the pad layer and the conductive connection layer; performing a selective ion implantation with an angle to make part of the poly-Si layer an undoped poly-Si layer; removing the undoped poly-Si layer to expose part of the conductive connection layer; etching the exposed conductive connection layer to form a recess; removing the poly-Si layer to make the exposed conductive connection layer a conductive connection strap; filling the recess with an insulation material to form a shallow trench isolation; exposing the conductive layer; and selectively removing the conductive layer to form a first conductive strap which forms the surface strap together with the conductive connection strap.
摘要翻译：一种形成表面带的方法包括：在其基板的表面上形成具有导电连接层的深沟槽电容器和与导电层接触的导电连接层; 形成覆盖所述焊盘层和所述导电连接层的多晶硅层; 以角度进行选择性离子注入，以使多晶硅层的一部分成为未掺杂的多晶硅层; 去除未掺杂的多晶硅层以暴露部分导电连接层; 蚀刻暴露的导电连接层以形成凹部; 去除所述多晶硅层以使所述暴露的导电连接层成为导电连接带; 用绝缘材料填充凹槽以形成浅沟槽隔离; 暴露导电层; 并且选择性地去除导电层以形成与导电连接带一起形成表面带的第一导电带。

2. 发明申请

US20090061580A1 METHOD OF FORMING FINFET DEVICE 有权
标题翻译：形成FINFET器件的方法
公开(公告)号：US20090061580A1
公开(公告)日：2009-03-05
申请号：US12030210
申请日：2008-02-13
申请人： Chih-Hao Cheng , Tzung-Han Lee
发明人： Chih-Hao Cheng , Tzung-Han Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879
摘要： The invention discloses a method of forming a finFET device. A hard mask layer is formed on an active area of a semiconductor substrate. A portion of the hard mask layer is etched to form a recess. A conformal gate defining layer is deposited on the recess and a tilt angle ion implantation process is performed. A part of the gate defining layer is removed to define a fin pattern. The fin pattern is subsequently transferred to the hard mask layer. The patterned hard mask layer having the fin pattern is utilized as an etching mask, and the semiconductor substrate is etched to form a fin structure.
摘要翻译：本发明公开了一种形成finFET器件的方法。在半导体衬底的有源区上形成硬掩模层。硬掩模层的一部分被蚀刻以形成凹部。在凹槽上沉积保形栅极限定层，并执行倾斜角度离子注入工艺。去除栅极限定层的一部分以限定鳍状图案。翅片图案随后转移到硬掩模层。将具有翅片图案的图案化的硬掩模层用作蚀刻掩模，并且蚀刻半导体衬底以形成翅片结构。

3. 发明申请

US20090001513A1 Semiconductor structure 有权
公开(公告)号：US20090001513A1
公开(公告)日：2009-01-01
申请号：US11949047
申请日：2007-12-03
申请人： Tzung-Han Lee , Chih-Hao Cheng , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chih-Hao Cheng , Chung-Yuan Lee
IPC分类号： H01L29/92
CPC分类号： H01L27/10891 , H01L27/10876
摘要： The present invention discloses a structure of a buried word line, which comprises a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer in the U-shape trench, a polysilicon layer on the U-shape gate dielectric layer, a conducting layer on the polysilicon layer, and a cover dielectric layer on the conducting layer. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect.

4. 发明申请

US20090001457A1 Semiconductor structure 审中-公开
标题翻译：半导体结构
公开(公告)号：US20090001457A1
公开(公告)日：2009-01-01
申请号：US11949048
申请日：2007-12-03
申请人： Tzung-Han Lee , Chih-Hao Cheng , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chih-Hao Cheng , Chung-Yuan Lee
IPC分类号： H01L29/78
CPC分类号： H01L27/10891 , H01L27/10876
摘要： The present invention discloses a semiconductor structure comprising a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer on the U-shape trench, a U-shape gate region on the U-shape gate dielectric layer, a conducting matter in the U-shape gate region, and a cover dielectric layer on the conducting matter. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect.
摘要翻译：本发明公开了一种半导体结构，其包括具有U形沟槽的半导体衬底，U形沟槽上的U形栅极电介质层，U形栅极电介质层上的U形栅极区域，导电材料在U形栅极区域和导电材料上的覆盖电介质层。半导体结构可以具有最小化的尺寸，并且当由此形成凹槽时，相应地提高了积分，而不会受到短沟道效应的影响。

5. 发明申请

US20080277709A1 DRAM STRUCTURE 审中-公开
标题翻译： DRAM结构
公开(公告)号：US20080277709A1
公开(公告)日：2008-11-13
申请号：US11872034
申请日：2007-10-14
申请人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/10867
摘要： A DRAM structure includes a substrate, a MOS transistor, a deep trench capacitor, a surface strap positioned on the surface of the substrate and interconnecting a drain of the MOS transistor and an electrode of the deep trench capacitor, wherein the sidewall and the top surface of the surface strap are covered with an insulating layer. A passing gate is positioned on the insulating layer.
摘要翻译： DRAM结构包括衬底，MOS晶体管，深沟槽电容器，位于衬底表面上的表面带，并将MOS晶体管的漏极和深沟槽电容器的电极互连，其中侧壁和顶表面的表面带被绝缘层覆盖。通孔位于绝缘层上。

6. 发明授权

US07633109B2 DRAM structure and method of making the same 有权
标题翻译： DRAM结构和制作方法
公开(公告)号：US07633109B2
公开(公告)日：2009-12-15
申请号：US11965769
申请日：2007-12-28
申请人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
发明人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/66621 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L29/4236
摘要： A DRAM structure has a substrate, a buried transistor with a fin structure, a trench capacitor, and a surface strap on the surface of the substrate. The surface strap is used to electrically connect a drain region to the trench capacitor.
摘要翻译： DRAM结构具有衬底，具有翅片结构的埋入晶体管，沟槽电容器和衬底表面上的表面带。表面带用于将漏极区域电连接到沟槽电容器。

7. 发明授权

US07615443B2 Method of forming finFET device 有权
标题翻译：形成finFET器件的方法
公开(公告)号：US07615443B2
公开(公告)日：2009-11-10
申请号：US12030210
申请日：2008-02-13
申请人： Chih-Hao Cheng , Tzung-Han Lee
发明人： Chih-Hao Cheng , Tzung-Han Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879
摘要： The invention discloses a method of forming a finFET device. A hard mask layer is formed on an active area of a semiconductor substrate. A portion of the hard mask layer is etched to form a recess. A conformal gate defining layer is deposited on the recess and a tilt angle ion implantation process is performed. A part of the gate defining layer is removed to define a fin pattern. The fin pattern is subsequently transferred to the hard mask layer. The patterned hard mask layer having the fin pattern is utilized as an etching mask, and the semiconductor substrate is etched to form a fin structure.
摘要翻译：本发明公开了一种形成finFET器件的方法。在半导体衬底的有源区上形成硬掩模层。硬掩模层的一部分被蚀刻以形成凹部。在凹槽上沉积保形栅极限定层，并执行倾斜角度离子注入工艺。去除栅极限定层的一部分以限定鳍状图案。翅片图案随后转移到硬掩模层。将具有翅片图案的图案化的硬掩模层用作蚀刻掩模，并且蚀刻半导体衬底以形成翅片结构。

8. 发明授权

US07586152B2 Semiconductor structure 有权
标题翻译：半导体结构
公开(公告)号：US07586152B2
公开(公告)日：2009-09-08
申请号：US11949047
申请日：2007-12-03
申请人： Tzung-Han Lee , Chih-Hao Cheng , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chih-Hao Cheng , Chung-Yuan Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10891 , H01L27/10876
摘要： The present invention discloses a structure of a buried word line, which comprises a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer in the U-shape trench, a polysilicon layer on the U-shape gate dielectric layer, a conducting layer on the polysilicon layer, and a cover dielectric layer on the conducting layer. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect.
摘要翻译：本发明公开了一种掩埋字线的结构，其包括具有U形沟槽的半导体衬底，U形沟槽中的U形栅极介电层，U形栅极介电层上的多晶硅层，多晶硅层上的导电层和导电层上的覆盖电介质层。半导体结构可以具有最小化的尺寸，并且当由此形成凹槽时，相应地提高了积分，而不会受到短沟道效应的影响。

9. 发明授权

US07557012B2 Method for forming surface strap 有权
标题翻译：形成表带的方法
公开(公告)号：US07557012B2
公开(公告)日：2009-07-07
申请号：US11940308
申请日：2007-11-14
申请人： Chih-Hao Cheng , Tzung-Han Lee , Chung-Yuan Lee
发明人： Chih-Hao Cheng , Tzung-Han Lee , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10867
摘要： A method for forming a surface strap includes forming a deep trench capacitor having a conductive connection layer on its surface in the substrate and the conductive connection layer in contact with the conductive layer; forming a poly-Si layer covering the pad layer and the conductive connection layer; performing a selective ion implantation with an angle to make part of the poly-Si layer an undoped poly-Si layer; removing the undoped poly-Si layer to expose part of the conductive connection layer; etching the exposed conductive connection layer to form a recess; removing the poly-Si layer to make the exposed conductive connection layer a conductive connection strap; filling the recess with an insulation material to form a shallow trench isolation; exposing the conductive layer; and selectively removing the conductive layer to form a first conductive strap which forms the surface strap together with the conductive connection strap.
摘要翻译：一种形成表面带的方法包括：在其基板的表面上形成具有导电连接层的深沟槽电容器和与导电层接触的导电连接层; 形成覆盖所述焊盘层和所述导电连接层的多晶硅层; 以角度进行选择性离子注入，以使多晶硅层的一部分成为未掺杂的多晶硅层; 去除未掺杂的多晶硅层以暴露部分导电连接层; 蚀刻暴露的导电连接层以形成凹部; 去除所述多晶硅层以使所述暴露的导电连接层成为导电连接带; 用绝缘材料填充凹槽以形成浅沟槽隔离; 暴露导电层; 并且选择性地去除导电层以形成与导电连接带一起形成表面带的第一导电带。

10. 发明申请

US20090008691A1 DRAM STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译： DRAM结构及其制作方法
公开(公告)号：US20090008691A1
公开(公告)日：2009-01-08
申请号：US11965769
申请日：2007-12-28
申请人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
发明人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
IPC分类号： H01L27/108
CPC分类号： H01L29/66621 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L29/4236
摘要： A DRAM structure has a substrate, a buried transistor with a fin structure, a trench capacitor, and a surface strap on the surface of the substrate. The surface strap is used to electrically connect a drain region to the trench capacitor.
摘要翻译： DRAM结构具有衬底，具有翅片结构的埋入晶体管，沟槽电容器和衬底表面上的表面带。表面带用于将漏极区域电连接到沟槽电容器。

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