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    • 2. 发明申请
    • RAIL TO RAIL COMPARATOR WITH WIDE HYSTERESIS AND MEMORY
    • 具有宽度滞后和记忆的轨道比较器
    • US20120306477A1
    • 2012-12-06
    • US13149399
    • 2011-05-31
    • Tyler DaigleJulie Lynn Stultz
    • Tyler DaigleJulie Lynn Stultz
    • G01R19/00
    • H03K5/2481
    • An apparatus comprises an input to receive a voltage, a threshold voltage circuit, a comparison circuit, and an output. The threshold voltage circuit provides an adjustable first threshold voltage at a first output and an adjustable second threshold voltage at a second output. The comparison circuit determines when the input voltage is greater than the first voltage threshold, including when the first voltage threshold is adjusted substantially up to a high supply voltage rail, and determines when the input voltage is less than the second voltage threshold, including when the second voltage threshold is adjusted substantially down to a low supply voltage rail. The output provides a first indication when the input voltage is greater than the first voltage threshold and to provide a second indication when the input voltage is less than the second voltage threshold.
    • 一种装置包括用于接收电压的输入,阈值电压电路,比较电路和输出。 阈值电压电路在第一输出端提供可调节的第一阈值电压,并在第二输出端提供可调节的第二阈值电压。 比较电路确定输入电压何时大于第一电压阈值,包括当第一电压阈值基本上被调节到高电源电压轨,并且确定输入电压何时小于第二电压阈值,包括何时 第二电压阈值被调节到低电源电压轨。 当输入电压大于第一电压阈值时,输出提供第一指示,并且当输入电压小于第二电压阈值时提供第二指示。
    • 3. 发明授权
    • Depletion-mode circuit
    • 耗电模式电路
    • US08610489B2
    • 2013-12-17
    • US13471832
    • 2012-05-15
    • Tyler DaigleJulie Lynn StultzKenneth P. Snowdon
    • Tyler DaigleJulie Lynn StultzKenneth P. Snowdon
    • H03K17/56
    • H03K17/06H03K2017/6875H03K2217/0054
    • This document discloses, among other things, a switch circuit that includes a depletion-mode field-effect transistor (DMFET) having an ON-state and an OFF-state, wherein the DMFET is configured to couple a first node to a second node in the ON-state, and wherein the DMFET is configured to isolate the first node from the second node in the OFF-state, a negative charge pump that is coupled to a gate terminal of the DMFET, the charge pump configured to supply a negative charge pump voltage to the gate terminal of the DMFET, and a negative discriminator coupled to the charge pump, the discriminator configured to compare a first voltage at the first node and a second voltage at the second node and determine the negative charge pump voltage based on the comparison.
    • 本文件尤其公开了一种开关电路,其包括具有导通状态和截止状态的耗尽型场效应晶体管(DMFET),其中DMFET被配置为将第一节点耦合到第二节点 所述导通状态,并且其中所述DMFET被配置为在所述关断状态下将所述第一节点与所述第二节点隔离,所述负电荷泵耦合到所述DMFET的栅极端子,所述电荷泵被配置为提供负电荷 对DMFET的栅极端子的泵浦电压和耦合到电荷泵的负鉴相器,鉴别器被配置为比较第一节点处的第一电压和第二节点处的第二电压,并且基于 比较。
    • 5. 发明授权
    • Rail to rail comparator with wide hysteresis and memory
    • 轨到轨比较器具有较大的滞后和记忆
    • US09059692B2
    • 2015-06-16
    • US13149399
    • 2011-05-31
    • Tyler DaigleJulie Lynn Stultz
    • Tyler DaigleJulie Lynn Stultz
    • G01R19/00H03K5/24
    • H03K5/2481
    • An apparatus comprises an input to receive a voltage, a threshold voltage circuit, a comparison circuit, and an output. The threshold voltage circuit provides an adjustable first threshold voltage at a first output and an adjustable second threshold voltage at a second output. The comparison circuit determines when the input voltage is greater than the first voltage threshold, including when the first voltage threshold is adjusted substantially up to a high supply voltage rail, and determines when the input voltage is less than the second voltage threshold, including when the second voltage threshold is adjusted substantially down to a low supply voltage rail. The output provides a first indication when the input voltage is greater than the first voltage threshold and to provide a second indication when the input voltage is less than the second voltage threshold.
    • 一种装置包括用于接收电压的输入,阈值电压电路,比较电路和输出。 阈值电压电路在第一输出端提供可调节的第一阈值电压,并在第二输出端提供可调节的第二阈值电压。 比较电路确定输入电压何时大于第一电压阈值,包括当第一电压阈值基本上被调节到高电源电压轨,并且确定输入电压何时小于第二电压阈值,包括何时 第二电压阈值被调节到低电源电压轨。 当输入电压大于第一电压阈值时,输出提供第一指示,并且当输入电压小于第二电压阈值时提供第二指示。
    • 6. 发明申请
    • DEPLETION-MODE CIRCUIT
    • 分离模式电路
    • US20130307591A1
    • 2013-11-21
    • US13471832
    • 2012-05-15
    • Tyler DaigleJulie Lynn StultzKenneth P. Snowdon
    • Tyler DaigleJulie Lynn StultzKenneth P. Snowdon
    • H03K17/06
    • H03K17/06H03K2017/6875H03K2217/0054
    • This document discloses, among other things, a switch circuit that includes a depletion-mode field-effect transistor (DMFET) having an ON-state and an OFF-state, wherein the DMFET is configured to couple a first node to a second node in the ON-state, and wherein the DMFET is configured to isolate the first node from the second node in the OFF-state, a negative charge pump that is coupled to a gate terminal of the DMFET, the charge pump configured to supply a negative charge pump voltage to the gate terminal of the DMFET, and a negative discriminator coupled to the charge pump, the discriminator configured to compare a first voltage at the first node and a second voltage at the second node and determine the negative charge pump voltage based on the comparison.
    • 本文件尤其公开了一种开关电路,其包括具有导通状态和截止状态的耗尽型场效应晶体管(DMFET),其中DMFET被配置为将第一节点耦合到第二节点 所述导通状态,并且其中所述DMFET被配置为在所述关断状态下将所述第一节点与所述第二节点隔离,所述负电荷泵耦合到所述DMFET的栅极端子,所述电荷泵被配置为提供负电荷 对DMFET的栅极端子的泵浦电压和耦合到电荷泵的负鉴相器,鉴别器被配置为比较第一节点处的第一电压和第二节点处的第二电压,并且基于 比较。
    • 8. 发明申请
    • HIGH INPUT VOLTAGE CHARGE PUMP
    • 高输入电压充电泵
    • US20130257522A1
    • 2013-10-03
    • US13435937
    • 2012-03-30
    • Tyler DaigleJulie Lynn Stultz
    • Tyler DaigleJulie Lynn Stultz
    • G05F3/02
    • H02M3/07
    • This document discusses, among other things, a charge pump circuit that includes an input, an output, a plurality of field effect transistors (FETs), each of the plurality FETs having a respective gate terminal, and at least two flying capacitors in electrical communication with at least one of the plurality of FETs. Each of the respective gate terminals is configured to receive a respective logic level shifted clock signal voltage. The at least two flying capacitors are configured to alternatingly charge and discharge in response to the logic level shifted clock signal voltages, and the at least two flying capacitors are configured to supply a voltage at the output that is different from a voltage at the input.
    • 本文件还讨论了一种电荷泵电路,其包括输入,输出,多个场效应晶体管(FET),多个FET中的每一个具有相应的栅极端子,以及至少两个电气通信中的飞行电容器 与多个FET中的至少一个FET连接。 每个相应的栅极端子被配置为接收相应的逻辑电平移位的时钟信号电压。 所述至少两个浮动电容器被配置为响应于所述逻辑电平移位的时钟信号电压而交替地充电和放电,并且所述至少两个飞越电容器被配置为在所述输出处提供不同于所述输入处的电压的电压。
    • 9. 发明授权
    • Reduced temperature dependent hysteretic comparator
    • 降低温度依赖性迟滞比较
    • US08598913B2
    • 2013-12-03
    • US13301990
    • 2011-11-22
    • Tyler DaigleAndrew M. Jordan
    • Tyler DaigleAndrew M. Jordan
    • H03K5/22
    • H03K3/3565H03K3/35613
    • This document discusses, among other things, apparatus and methods for controlling a hysteresis range of a voltage comparator. In an example, an apparatus can include an amplifier having a temperature dependency, a comparator configured to receive first and second currents and to provide an output voltage indicative of a hysteretic comparison of the first and second input voltages, wherein a range of hysteresis of the apparatus is controlled over a range of temperatures. In an example, the amplifier can be configured to receive first and second input voltages and to provide the first and second currents.
    • 本文件还讨论了用于控制电压比较器的滞后范围的装置和方法。 在一个示例中,装置可以包括具有温度依赖性的放大器,配置成接收第一和第二电流并提供指示第一和第二输入电压的迟滞比较的输出电压的比较器,其中, 装置在一定温度范围内被控制。 在一个示例中,放大器可被配置为接收第一和第二输入电压并提供第一和第二电流。
    • 10. 发明授权
    • Methods and apparatus for self-trim calibration of an oscillator
    • 振荡器自校正校准的方法和装置
    • US08564375B2
    • 2013-10-22
    • US13341490
    • 2011-12-30
    • John R. TurnerTyler Daigle
    • John R. TurnerTyler Daigle
    • H03L7/24
    • H03K3/02315H03L7/0805H03L7/099H03L2207/50
    • In one general aspect, an apparatus can include a reference oscillator counter circuit configured to produce a reference oscillator count value based on a reference oscillator signal, and a target oscillator counter circuit configured to produce a target oscillator count value based on a target oscillator signal where the target oscillator signal has a frequency targeted for calibration against a frequency of the reference oscillator signal. The apparatus can include a difference circuit configured to calculate a difference between the reference oscillator counter value and the target oscillator counter value, and a summation circuit configured to define a trim code based on only a portion of bit values from the difference.
    • 在一个一般方面,一种装置可以包括:参考振荡器计数器电路,被配置为基于参考振荡器信号产生参考振荡器计数值;以及目标振荡器计数器电路,被配置为基于目标振荡器信号产生目标振荡器计数值, 目标振荡器信号具有针对基准振荡器信号的频率进行校准的频率。 该装置可以包括被配置为计算参考振荡器计数器值和目标振荡器计数器值之间的差的差分电路,以及被配置为仅基于来自差值的位值的一部分来定义修剪码的求和电路。