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1. 发明授权

US6025733A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US6025733A
公开(公告)日：2000-02-15
申请号：US18055
申请日：1998-02-03
申请人： Tuyoshi Saitoh , Akira Kitaguchi , Masaaki Matsuo , Makoto Hatakenaka , Toshio Nakano , Yuko Sudo
发明人： Tuyoshi Saitoh , Akira Kitaguchi , Masaaki Matsuo , Makoto Hatakenaka , Toshio Nakano , Yuko Sudo
IPC分类号： G01R31/28 , G11C29/02 , G11C29/48 , H01L21/66 , H01L21/82 , H01L27/10 , G01R31/26
CPC分类号： G11C29/48 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/48463
摘要： A semiconductor memory device includes two subcircuits each including a memory circuit, a semiconductor circuit, and a logical circuit. Connection pads are divided into only two parallel rows located along the outer periphery of the semiconductor memory device. Each of the pads may include a probe region against which a probe is pressed for testing the semiconductor memory circuit, and a wire region to which a wire is connected upon packaging.
摘要翻译：半导体存储器件包括两个子电路，每个子电路包括存储电路，半导体电路和逻辑电路。连接焊盘被分成仅沿着半导体存储器件的外围设置的两个平行的行。每个焊盘可以包括：探针被按压的探针区域，用于测试半导体存储器电路;以及导线区域，在包装时连接导线。

2. 发明授权

US6092227A Test circuit 失效
标题翻译：测试电路
公开(公告)号：US6092227A
公开(公告)日：2000-07-18
申请号：US18934
申请日：1998-02-05
申请人： Hideki Toki , Akira Kitaguchi , Makoto Hatakenaka , Kiyoyuki Shiroshima , Masaaki Matsuo , Tsuyoshi Saitoh
发明人： Hideki Toki , Akira Kitaguchi , Makoto Hatakenaka , Kiyoyuki Shiroshima , Masaaki Matsuo , Tsuyoshi Saitoh
IPC分类号： G01R31/28 , G06F11/22 , G11C11/413 , G11C29/10 , G11C29/34 , G11C29/36 , G11C29/38 , G11C29/56
CPC分类号： G11C29/34 , G11C29/36 , G11C29/38 , G11C29/10
摘要： A test circuit includes a writing unit that outputs m-bit data captured upon receipt of a clock signal, branches the m-bit data n identical m-bit data signals, and stores the n m-bit data signals in a memory device. A function determining unit reads the n m-bit data signals from the memory, compares one of the n m-bit data signals to an m-bit expected value, and determines coincidence or non-coincidence between the n m-bit data signal and an expected value.
摘要翻译：测试电路包括写入单元，其输出接收到时钟信号时捕获的m位数据，分配m位数据n个相同的m位数据信号，并将n个m位数据信号存储在存储器件中。功能确定单元从存储器读取n个m位数据信号，将n个m位数据信号中的一个与m位预期值进行比较，并且确定n个m位数据信号和一个预期的价值。

3. 发明授权

US6043522A Field effect transistor array including doped two-cell isolation region for preventing latchup 失效
标题翻译：场效应晶体管阵列包括用于防止闭锁的掺杂的二单元隔离区
公开(公告)号：US6043522A
公开(公告)日：2000-03-28
申请号：US61090
申请日：1998-04-16
申请人： Michio Nakajima , Makoto Hatakenaka , Akira Kitaguchi , Kiyoyuki Shiroshima , Takekazu Yamashita , Masaaki Matsuo
发明人： Michio Nakajima , Makoto Hatakenaka , Akira Kitaguchi , Kiyoyuki Shiroshima , Takekazu Yamashita , Masaaki Matsuo
IPC分类号： H01L21/761 , H01L21/8238 , H01L27/092 , H01L27/10 , H01L27/105
CPC分类号： H01L27/105 , H01L21/761 , Y10S257/901 , Y10S257/909
摘要： A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.
摘要翻译：能够解决现有的半导体器件的问题的半导体器件的原因在于，由于包括一对相邻地设置的一对N阱和P阱的每个单元需要单独地闭锁的对策，所以不能期望高密度积分。高密度集成防止锁定的有效对策。本半导体装置将N个阱和P个阱的排列方向相邻的两个电池相反地配置，使得两个相邻电池的两个P阱（或两个N阱）相继配置，并且包括隔离层延伸穿过两个相邻的电池以封闭两个连续设置的P阱，从而将两个P阱与衬底共同隔离。

4. 发明授权

US5973953A Semiconductor memory device having improved bit line structure 失效
标题翻译：具有改进的位线结构的半导体存储器件
公开(公告)号：US5973953A
公开(公告)日：1999-10-26
申请号：US38278
申请日：1998-03-11
申请人： Takekazu Yamashita , Kiyoyuki Shiroshima , Michio Nakajima , Makoto Hatakenaka , Hideki Toki , Tuyoshi Saitoh
发明人： Takekazu Yamashita , Kiyoyuki Shiroshima , Michio Nakajima , Makoto Hatakenaka , Hideki Toki , Tuyoshi Saitoh
IPC分类号： H01L21/3205 , G11C5/06 , H01L21/8242 , H01L23/52 , H01L27/108
CPC分类号： G11C5/063
摘要： A semiconductor memory device is constituted such that, when a first wiring layer provides a bit line of a first common complementary data line pair and a third wiring layer provides a bit line of a second common complementary data line pair, a second wiring layer makes an overlapped area between the bit line and the bit bar line of the second common complementary dada line pair equal to the bit line of the first common complementary data line pair and also an overlapped area between the bit line and the bit bar line of the first common complementary data line pair equal to the bit line of the second common complementary data line pair.
摘要翻译：半导体存储器件被构造成使得当第一布线层提供第一公共互补数据线对的位线并且第三布线层提供第二公共互补数据线对的位线时，第二布线层使得第二公共互补数据线对的位线和位线之间的重叠区域等于第一公共互补数据线对的位线，以及第一公共补充数据线对的位线和位线之间的重叠区域互补数据线对等于第二公共互补数据线对的位线。

5. 发明授权

US6040614A Semiconductor integrated circuit including a capacitor and a fuse element 失效
标题翻译：包括电容器和熔丝元件的半导体集成电路
公开(公告)号：US6040614A
公开(公告)日：2000-03-21
申请号：US33611
申请日：1998-03-03
申请人： Akira Kitaguchi , Makoto Hatakenaka , Michio Nakajima , Kaoru Motonami , Kiyoyuki Shiroshima , Takekazu Yamashita
发明人： Akira Kitaguchi , Makoto Hatakenaka , Michio Nakajima , Kaoru Motonami , Kiyoyuki Shiroshima , Takekazu Yamashita
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/525 , H01L27/105 , H01L27/108 , H01L29/40
CPC分类号： H01L23/5258 , H01L27/105 , H01L27/108 , H01L2924/0002
摘要： A semiconductor integrated circuit includes a fuse element located on an insulating layer. The surface of the insulating layer is substantially smooth. The insulating layer is located over a capacitor. Wiring is located on the insulation layer. The fuse element and the wiring include the same material.
摘要翻译：半导体集成电路包括位于绝缘层上的熔丝元件。绝缘层的表面基本上是光滑的。绝缘层位于电容器的上方。接线位于绝缘层上。熔丝元件和布线包括相同的材料。

6. 发明授权

US06724237B2 Semiconductor integrated circuit for multi-chip package with means to optimize internal drive capacity 有权
标题翻译：用于多芯片封装的半导体集成电路，具有优化内部驱动能力的手段
公开(公告)号：US06724237B2
公开(公告)日：2004-04-20
申请号：US10212842
申请日：2002-08-07
申请人： Takekazu Yamashita , Makoto Hatakenaka , Manabu Miura
发明人： Takekazu Yamashita , Makoto Hatakenaka , Manabu Miura
IPC分类号： G01R3127
CPC分类号： H03K19/017581 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H03K17/164 , Y10T307/50 , H01L2924/00014
摘要： A semiconductor integrated circuit can variably set the driving power of all or part of internal input/output terminals and internal output terminals used within a multi-chip package. It can increase the driving power at an individual wafer test before packaging to sufficiently drive a load connected between a tester and the internal input/output terminals and internal output terminals, and can reduce the driving power after packaging. It can prevent noise and power consumption from being increased.
摘要翻译：半导体集成电路可以可变地设置在多芯片封装内使用的内部输入/输出端子和内部输出端子的全部或部分的驱动功率。在包装之前，可以在单个晶片测试时增加驱动功率，以充分驱动连接在测试器与内部输入/输出端子和内部输出端子之间的负载，并且可以降低封装后的驱动功率。可以防止噪音和功耗的增加。

7. 发明授权

US5910181A Semiconductor integrated circuit device comprising synchronous DRAM core and logic circuit integrated into a single chip and method of testing the synchronous DRAM core 失效
标题翻译：半导体集成电路器件包括同步DRAM核心和逻辑电路集成到单个芯片中以及测试同步DRAM内核的方法
公开(公告)号：US5910181A
公开(公告)日：1999-06-08
申请号：US964236
申请日：1997-11-04
申请人： Makoto Hatakenaka , Akira Yamazaki , Shigeki Tomishima , Tadato Yamagata
发明人： Makoto Hatakenaka , Akira Yamazaki , Shigeki Tomishima , Tadato Yamagata
IPC分类号： G11C11/407 , G11C11/401 , G11C29/02 , G11C29/14 , G11C29/16 , G11C29/48 , G06F11/00
CPC分类号： G11C29/16 , G11C29/48
摘要： A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector, and are provided to the core unit of the synchronous dynamic random access memory for testing.
摘要翻译：半导体集成电路器件包括集成在单个半导体芯片上的逻辑电路和包括核心单元的同步动态随机存取存储器。半导体集成电路装置包括：同步动态随机存取存储器控制电路，其从逻辑电路接收用于同步动态随机存取存储器的外部控制信号，并将内部控制信号输出到同步动态随机存取存储器的核心单元。对于半导体集成电路器件的测试，通过外部端子提供外部测试信号。外部测试信号由选择器选择，并提供给同步动态随机存取存储器的核心单元进行测试。

8. 发明授权

US5491438A Synchronized clock generating apparatus 失效
标题翻译：同步时钟发生装置
公开(公告)号：US5491438A
公开(公告)日：1996-02-13
申请号：US289837
申请日：1994-08-12
申请人： Yukio Miyazaki , Takenori Okitaka , Makoto Hatakenaka , Junji Mano
发明人： Yukio Miyazaki , Takenori Okitaka , Makoto Hatakenaka , Junji Mano
IPC分类号： G06F1/10 , H03K5/00 , H03K5/13 , H04L7/033 , H03L7/00
CPC分类号： H04L7/0338 , G06F1/10 , H03K5/133 , H03K2005/00234
摘要： A synchronized clock generating apparatus includes a delayed clock generating circuit including a plurality of serially connected delaying elements for generating delayed clock signals delayed successively relative to an incoming basic clock signal. Storage means includes a plurality of storage elements storing therein a predetermined level in response to transitions occurring in associated ones of said basic and delayed clock signals after a trigger signal which is asynchronous with the basic clock signal is applied thereto. A clock selection logic circuit is controlled by the output signal of the storage means for detecting the clock signal transition occurring closest in time to the application of the asynchronous trigger signal, and for selecting a desired one of said clock signals, based on the result of the detection, as a synchronized clock signal output.
摘要翻译：同步时钟发生装置包括延迟时钟产生电路，其包括多个串行连接的延迟元件，用于产生相对于输入的基本时钟信号连续延迟的延迟时钟信号。存储装置包括多个存储元件，其中，在施加与基本时钟信号异步的触发信号之后，响应于在相关联的所述基本和延迟的时钟信号中发生的转换，存储其中的预定电平。时钟选择逻辑电路由存储装置的输出信号控制，用于检测在施加异步触发信号时在时间上最近发生的时钟信号转换，并且基于所述时钟信号的结果来选择期望的一个时钟信号检测，作为同步时钟信号输出。

9. 发明授权

US07716410B2 Information device including main processing circuit, interface circuit, and microcomputer 有权
标题翻译：信息设备包括主处理电路，接口电路和微机
公开(公告)号：US07716410B2
公开(公告)日：2010-05-11
申请号：US11584550
申请日：2006-10-23
申请人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
发明人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
IPC分类号： G06F13/14
CPC分类号： H04N5/04 , G09G5/006 , H04N5/775 , H04N5/85
摘要： An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.
摘要翻译：信息装置包括用于执行与信息装置中的主要功能相关的信号处理的主处理电路，用于控制主处理电路的主微型计算机，用于与信息装置的外部进行接口的接收机电路，以及用于控制接收机电路，接口微型计算机与主微型计算机分开设置。

10. 再颁专利

USRE39579E1 Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system 有权
标题翻译：半导体集成电路器件包括具有集成到单个芯片中的命令解码系统和逻辑电路的RAM以及具有命令解码系统的RAM的测试方法
公开(公告)号：USRE39579E1
公开(公告)日：2007-04-17
申请号：US09871978
申请日：2001-06-04
申请人： Makoto Hatakenaka , Akira Yamazaki , Shigeki Tomishima , Tadato Yamagata
发明人： Makoto Hatakenaka , Akira Yamazaki , Shigeki Tomishima , Tadato Yamagata
IPC分类号： G06F11/00
CPC分类号： G06F11/00
摘要： A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector and are provided to the core unit of the synchronous dynamic random access memory for testing.
摘要翻译：半导体集成电路器件包括集成在单个半导体芯片上的逻辑电路和包括核心单元的同步动态随机存取存储器。半导体集成电路装置包括：同步动态随机存取存储器控制电路，其从逻辑电路接收用于同步动态随机存取存储器的外部控制信号，并将内部控制信号输出到同步动态随机存取存储器的核心单元。对于半导体集成电路器件的测试，通过外部端子提供外部测试信号。外部测试信号由选择器选择，并提供给同步动态随机存取存储器的核心单元进行测试。

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