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1. 发明授权

US06756803B2 Semiconductor device downsizing its built-in driver 失效
标题翻译：半导体器件缩小其内置驱动器
公开(公告)号：US06756803B2
公开(公告)日：2004-06-29
申请号：US10330072
申请日：2002-12-30
申请人： Manabu Miura , Makoto Hatakenaka , Takekazu Yamashita
发明人： Manabu Miura , Makoto Hatakenaka , Takekazu Yamashita
IPC分类号： G01R3102
CPC分类号： G01R31/2884 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device includes a first pad, a second pad, a first buffer and a second buffer. The first pad is connected to another semiconductor device in a multi-chip package, and the second pad makes a probing connection in a wafer test. The first buffer drives the another semiconductor device connected to the first pad. The second buffer, being driven by the first buffer, drives a load capacitance of a tester connected to the second pad with the driving power greater than the driving power of the first buffer, and has its active/inactive state controlled by a control signal. The semiconductor device can provide the driving power necessary for the wafer test, and drive the another semiconductor device with preventing generation of drive noise and suppressing current consumption in the normal operation of the multi-chip package.
摘要翻译：半导体器件包括第一焊盘，第二焊盘，第一缓冲器和第二缓冲器。第一焊盘以多芯片封装连接到另一半导体器件，并且第二焊盘在晶片测试中进行探测连接。第一缓冲器驱动连接到第一焊盘的另一个半导体器件。由第一缓冲器驱动的第二缓冲器以大于第一缓冲器的驱动功率的驱动功率驱动连接到第二焊盘的测试仪的负载电容，并且由控制信号控制其主动/不活动状态。半导体器件可以提供晶片测试所需的驱动功率，并驱动另一半导体器件，防止产生驱动噪声并抑制多芯片封装的正常工作中的电流消耗。

2. 发明授权

US06724237B2 Semiconductor integrated circuit for multi-chip package with means to optimize internal drive capacity 有权
标题翻译：用于多芯片封装的半导体集成电路，具有优化内部驱动能力的手段
公开(公告)号：US06724237B2
公开(公告)日：2004-04-20
申请号：US10212842
申请日：2002-08-07
申请人： Takekazu Yamashita , Makoto Hatakenaka , Manabu Miura
发明人： Takekazu Yamashita , Makoto Hatakenaka , Manabu Miura
IPC分类号： G01R3127
CPC分类号： H03K19/017581 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H03K17/164 , Y10T307/50 , H01L2924/00014
摘要： A semiconductor integrated circuit can variably set the driving power of all or part of internal input/output terminals and internal output terminals used within a multi-chip package. It can increase the driving power at an individual wafer test before packaging to sufficiently drive a load connected between a tester and the internal input/output terminals and internal output terminals, and can reduce the driving power after packaging. It can prevent noise and power consumption from being increased.
摘要翻译：半导体集成电路可以可变地设置在多芯片封装内使用的内部输入/输出端子和内部输出端子的全部或部分的驱动功率。在包装之前，可以在单个晶片测试时增加驱动功率，以充分驱动连接在测试器与内部输入/输出端子和内部输出端子之间的负载，并且可以降低封装后的驱动功率。可以防止噪音和功耗的增加。

3. 发明授权

US5949268A Variable delay circuit for varying delay time and pulse width 失效
标题翻译：可变延迟电路，用于改变延迟时间和脉冲宽度
公开(公告)号：US5949268A
公开(公告)日：1999-09-07
申请号：US914803
申请日：1997-08-15
申请人： Manabu Miura , Makoto Hatakenaka
发明人： Manabu Miura , Makoto Hatakenaka
IPC分类号： H03K5/04 , H03K5/13 , H03K17/16 , H03K17/687
CPC分类号： H03K17/164 , H03K5/131
摘要： A variable delay circuit for controlling delay time includes P channel transistors connected in parallel, with respective source electrodes connected to a power supply, respective drain electrodes connected to an output terminal for providing delayed signal, and respective gate electrodes connected to respective control signal input terminals for receiving control signals. The circuit further includes N channel transistors with respective source electrodes connected to ground, respective drain electrodes connected to the output terminal, and respective gate electrode connected to the respective control signal input terminals. Identical or mutually inverted data signals or control signals are supplied to the respective gate electrodes of the P channel transistors and the respective gate electrodes of the N channel transistors.
摘要翻译：用于控制延迟时间的可变延迟电路包括并联连接的P沟道晶体管，各个源电极连接到电源，连接到用于提供延迟信号的输出端的相应漏电极以及连接到相应控制信号输入端的各个栅电极用于接收控制信号。电路还包括具有连接到地的各个源极的N沟道晶体管，连接到输出端的相应的漏极和连接到各个控制信号输入端的相应的栅电极。将相同或相互反转的数据信号或控制信号提供给P沟道晶体管的各个栅电极和N沟道晶体管的各个栅电极。

4. 发明授权

US06715117B2 Method of testing a semiconductor memory device 有权
标题翻译：测试半导体存储器件的方法
公开(公告)号：US06715117B2
公开(公告)日：2004-03-30
申请号：US09761847
申请日：2001-01-18
申请人： Atsuo Mangyo , Manabu Miura , Makoto Hatakenaka
发明人： Atsuo Mangyo , Manabu Miura , Makoto Hatakenaka
IPC分类号： G11C2900
CPC分类号： G11C29/48 , G11C29/08
摘要： A method for testing a semiconductor memory device according to one embodiment comprises the steps of: checking data in all addresses of the semiconductor memory device for correctness in-units of m×n bits: ending if it is determined that data in all the semiconductor memory device; if there is a defective address, comparing each m-bit data constituting the (m×n)-bit data corresponding to the defective address with its expected value; and if the comparison result indicates that the m-bit data is erroneous, determining whether the defective semiconductor memory device can be repaired. Due to this step, man hours required for testing a semiconductor memory device having a wide data bus of an (m×n)-bit width can be considerably reduced.
摘要翻译：根据一个实施例的用于测试半导体存储器件的方法包括以下步骤：检查半导体存储器件的所有地址中的数据，以确定m×n位的单位的正确性：如果确定所有半导体存储器件中的数据，则结束; 如果存在缺陷地址，则将构成与缺陷地址相对应的（m×n）位数据的每个m位数据与其期望值进行比较; 并且如果比较结果表明m位数据是错误的，则确定是否可以修复有缺陷的半导体存储器件。由于该步骤，可以显着地减少测试具有宽（mxn）位宽的数据总线的半导体存储器件所需的工时。

5. 发明授权

US06570572B1 Line delay generator using one-port RAM 有权
标题翻译：线路延迟发生器使用单端口RAM
公开(公告)号：US06570572B1
公开(公告)日：2003-05-27
申请号：US09303623
申请日：1999-05-03
申请人： Manabu Miura , Makoto Hatakenaka , Mikio Tada
发明人： Manabu Miura , Makoto Hatakenaka , Mikio Tada
IPC分类号： G09G539
CPC分类号： G06F5/10 , H04N5/14
摘要： A line delay generator including a packetizing circuit, one port RAM and a RAM controller. The RAM controller provides the one port RAM with a write command to write packet data generated by the packetizing circuit, and with a read command to read any one or more packet data currently stored in the one port RAM, and output them as line delay data. The line delay generator can solve a problem involved in a conventional line delay generator in that because m (positive integer) two-port FIFOs must be connected in cascade to generate m line delay data, the FIFO memory becomes bulky.
摘要翻译：线延迟发生器，包括分组化电路，一个端口RAM和一个RAM控制器。 RAM控制器为单端口RAM提供写入命令，以写入由分组化电路产生的分组数据，并且读取命令读取当前存储在一个端口RAM中的任何一个或多个分组数据，并将其作为行延迟数据输出。线路延迟发生器可以解决传统线路延迟发生器中涉及的问题，因为m（正整数）双端口FIFO必须级联连接以产生m线延迟数据，因此FIFO存储器变得庞大。

6. 发明授权

US06512707B2 Semiconductor integrated circuit device allowing accurate evaluation of access time of memory core contained therein and access time evaluating method 有权
公开(公告)号：US06512707B2
公开(公告)日：2003-01-28
申请号：US09837164
申请日：2001-04-19
申请人： Manabu Miura , Makoto Hatakenaka
发明人： Manabu Miura , Makoto Hatakenaka
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C11/401 , G11C29/50 , G11C29/50012
摘要： An external clock signal is transmitted as a clock signal to a memory core through a first signal transmitting path. In response to activation of the clock signal CLK, memory core starts a read operation. Read data output from memory core is latched by a latch circuit. An external signal designating a latch timing is transmitted as a latch timing signal to the latch circuit through a second signal transmitting path. A delay circuit is provided in at least one of the first and second signal transmitting paths, so that the first and second signal transmitting paths come to have the same signal delay.

7. 发明申请

US20060130807A1 Control apparatus for an internal combustion engine 审中-公开
标题翻译：一种用于内燃机的控制装置
公开(公告)号：US20060130807A1
公开(公告)日：2006-06-22
申请号：US11314276
申请日：2005-12-21
申请人： Manabu Miura
发明人： Manabu Miura
IPC分类号： F02D41/30
CPC分类号： F02D31/001 , F02D41/083
摘要： To allow control of the revolution with good response during idling operation even if the air excess coefficient is reduced, thereby reducing the isovolumetric level in a diesel engine, the isovolumetric level CVOL is estimated based on at least one of air excess coefficient, fuel ignition timing, and pressure end temperature inside a cylinder. The engine load FMOT is estimated based on at least one of intake air pressure, EGR rate, air excess coefficient, water temperature, and auxiliary load. The idle injection rate is calculated from the isovolumetric level CVOL and engine load FMOT.
摘要翻译：为了在怠速运转期间能够在空转操作期间具有良好响应的旋转控制，即使空气过剩系数降低，从而降低柴油发动机的等容积水平，基于空气过剩系数，燃料点火正时中的至少一个来估计等容量水平CVOL ，以及气缸内的压力结束温度。基于进气压力，EGR率，空气过剩系数，水温和辅助负荷中的至少一个来估计发动机负荷FMOT。怠速喷射速率由等体积水平CVOL和发动机负载FMOT计算。

8. 发明申请

US20050188681A1 Deterioration diagnosis of diesel particulate filter 失效
标题翻译：柴油颗粒过滤器的劣化诊断
公开(公告)号：US20050188681A1
公开(公告)日：2005-09-01
申请号：US11063869
申请日：2005-02-24
申请人： Masahiko Emi , Manabu Miura
发明人： Masahiko Emi , Manabu Miura
IPC分类号： F01N3/00 , F01N3/023 , F01N7/00 , F01N11/00 , F02D41/14
CPC分类号： F01N3/023 , F01N3/0231 , F01N11/007 , F01N2330/06 , F01N2550/04 , F02D41/1441 , F02D41/1495 , Y02T10/47
摘要： A filter (14) traps particulate matter contained in the exhaust gas of a diesel engine (1). The filter (14) is regenerated by burning the trapped particulate matter through an operation to raise the exhaust gas temperature. An oxidation catalyst which promotes combustion of the particulate matter is coated onto the filter (14). The oxygen concentration of the exhaust gas upstream of the filter (14) and the oxygen concentration of the exhaust gas downstream of the filter (14) during the regeneration period are detected using universal exhaust gas oxygen sensors (17, 16). A controller (25) determines a substantial regeneration period on the basis of the difference between these oxygen concentrations, and by comparing a maximum value of the difference between the oxygen concentrations during the substantial regeneration period with a predetermined threshold, determines deterioration of the filter (14) with a high degree of precision.
摘要翻译：过滤器（14）捕获包含在柴油发动机（1）的废气中的颗粒物质。过滤器（14）通过燃烧被捕获的颗粒物质进行再生来提高废气温度。促进颗粒物质燃烧的氧化催化剂被涂覆在过滤器（14）上。使用通用排气氧传感器（17,16）检测在再生期间过滤器（14）上游的废气的氧浓度和过滤器（14）下游的排气的氧浓度。控制器（25）基于这些氧气浓度之间的差异确定实质上的再生时间，并且通过将实质再生期间的氧浓度之间的差的最大值与预定阈值进行比较，确定过滤器的劣化（ 14）精度高。

9. 发明申请

US20050188679A1 Deterioration diagnosing device and diagnosing method for exhaust gas purification catalyst 失效
标题翻译：废气净化催化剂恶化诊断装置及诊断方法
公开(公告)号：US20050188679A1
公开(公告)日：2005-09-01
申请号：US11059480
申请日：2005-02-17
申请人： Manabu Miura
发明人： Manabu Miura
IPC分类号： G01N27/409 , F01N3/00 , F01N3/08 , F01N3/20 , F01N3/28 , F01N11/00 , F02B37/24 , F02D41/14 , F02D45/00 , G01N27/26 , F01N7/00
CPC分类号： F01N3/0835 , F01N3/0821 , F01N11/007 , F01N2550/02 , F01N2550/03 , F01N2900/0422 , F02B37/24 , F02D41/1441 , F02D41/1456 , F02D41/1495 , Y02T10/20 , Y02T10/47
摘要： To determine whether an exhaust gas purification catalyst (42) of an engine (1) has deteriorated, a characteristic of exhaust gas on an upstream side of the catalyst (42) is detected, a characteristic of the exhaust gas on a downstream side of the catalyst (42) is detected, and when the engine (1) operates at a lean air-fuel ratio, a value expressing a difference in the oxygen concentration on the upstream side and downstream side of the catalyst (42) (an average excess air ratio difference) is calculated from the two detected values. When the value expressing the difference in the oxygen concentration is smaller than a deterioration determination threshold calculated in accordance with a quantity of state of the catalyst (42), the catalyst (42) is determined to have deteriorated.
摘要翻译：为了确定发动机（1）的废气净化催化剂（42）是否劣化，检测到催化剂（42）的上游侧的废气的特性，排气的下游侧的特性检测催化剂（42），当发动机（1）以稀空燃比运转时，表示催化剂（42）的上游侧和下游侧的氧浓度差（平均过量空气比率差）由两个检测值计算。当表示氧浓度差的值小于根据催化剂（42）的状态量计算的劣化判定阈值时，判定催化剂（42）劣化。

10. 发明申请

US20050022778A1 Engine fuel injection control system 失效
公开(公告)号：US20050022778A1
公开(公告)日：2005-02-03
申请号：US10883654
申请日：2004-07-06
申请人： Manabu Miura
发明人： Manabu Miura
IPC分类号： F02M45/04 , F02D41/02 , F02D41/38 , F02D41/40
CPC分类号： F02D41/401 , F02D41/027 , F02D41/0275 , F02D41/403 , Y02T10/44
摘要： An engine fuel injection control system is configured to alleviate the torque fluctuation that occurs due to deviation in a pilot injection timing when the excess air ratio is changed suddenly from lean to rich. When the excess air ratio changes by a large amount, the pilot injection interval is changed in accordance with the actual excess air ratio by executing an interpolation calculation based on the target excess air ratio and the actual excess air ratio. During the transient period when the actual excess air ratio is converging toward the target excess air ratio, the pilot injection interval is changed in accordance with the change in the actual excess air ratio. As a result, it is possible to alleviate torque fluctuation by suppressing the tendency of the pilot injection interval to change rapidly in a step-like manner between target values before and after the excess air ratio changes.

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