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1. 发明授权

US07855384B2 SIC semiconductor device and method for manufacturing the same 有权
标题翻译： SIC半导体器件及其制造方法
公开(公告)号：US07855384B2
公开(公告)日：2010-12-21
申请号：US11783611
申请日：2007-04-10
申请人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
发明人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
IPC分类号： H01L29/04 , H01L29/94
CPC分类号： H01L29/1608 , H01L29/0843 , H01L29/1066 , H01L29/8083 , H01L29/872
摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.
摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

2. 发明申请

US20070241338A1 SIC semiconductor device and method for manufacturing the same 有权
标题翻译： SIC半导体器件及其制造方法
公开(公告)号：US20070241338A1
公开(公告)日：2007-10-18
申请号：US11783611
申请日：2007-04-10
申请人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
发明人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
IPC分类号： H01L31/0312
CPC分类号： H01L29/1608 , H01L29/0843 , H01L29/1066 , H01L29/8083 , H01L29/872
摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.
摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

3. 发明授权

US07307313B2 Semiconductor device including a vertical field effect transistor, having trenches, and a diode 有权
标题翻译：包括具有沟槽的垂直场效应晶体管和二极管的半导体器件
公开(公告)号：US07307313B2
公开(公告)日：2007-12-11
申请号：US11206212
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
IPC分类号： H01L29/76
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.
摘要翻译：半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽，沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管，在第二沟槽之间的第二表面上形成的结。

4. 发明申请

US20060071217A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060071217A1
公开(公告)日：2006-04-06
申请号：US11206271
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
IPC分类号： H01L31/0312
CPC分类号： H01L21/823487 , H01L29/7722
摘要： A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.
摘要翻译：半导体器件包括：垂直场效应晶体管，其具有在基板基底中的第一导电类型的衬底;形成在衬底的第一表面上的漏电极，形成在衬底的第二表面上的第一导电类型的外延层; 在半导体基底上形成的第一导电类型的源极区域，与源极区欧姆接触的源欧姆接触金属膜，从半导体基底的第二表面形成的沟槽和沿着沟槽形成的第二导电类型的栅极区域。半导体器件还包括与沟槽底部的栅极区域的引出层欧姆接触并上升到半导体基底的第二表面的栅极上升金属膜，以及连接到来自半导体基底的第二表面的栅极上升金属膜。

5. 发明授权

US07663181B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07663181B2
公开(公告)日：2010-02-16
申请号：US11206271
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
IPC分类号： H01L29/72
CPC分类号： H01L21/823487 , H01L29/7722
摘要： A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.
摘要翻译：半导体器件包括：垂直场效应晶体管，其具有在基板基底中的第一导电类型的衬底;形成在衬底的第一表面上的漏电极，形成在衬底的第二表面上的第一导电类型的外延层; 在半导体基底上形成的第一导电类型的源极区域，与源极区欧姆接触的源欧姆接触金属膜，从半导体基底的第二表面形成的沟槽和沿着沟槽形成的第二导电类型的栅极区域。半导体器件还包括与沟槽底部的栅极区域的引出层欧姆接触并上升到半导体基底的第二表面的栅极上升金属膜，以及连接到来自半导体基底的第二表面的栅极上升金属膜。

6. 发明申请

US20060076613A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060076613A1
公开(公告)日：2006-04-13
申请号：US11206212
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Malhan
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Malhan
IPC分类号： H01L29/94
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.
摘要翻译：半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽，沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管，在第二沟槽之间的第二表面上形成的结。

7. 发明授权

US06696323B2 Method of manufacturing semiconductor device having trench filled up with gate electrode 有权
标题翻译：制造具有填充有栅电极的沟槽的半导体器件的方法
公开(公告)号：US06696323B2
公开(公告)日：2004-02-24
申请号：US10340746
申请日：2003-01-13
申请人： Hitoshi Yamaguchi , Toshio Sakakibara , Jun Sakakibara , Takumi Shibata , Toshiyuki Morishita
发明人： Hitoshi Yamaguchi , Toshio Sakakibara , Jun Sakakibara , Takumi Shibata , Toshiyuki Morishita
IPC分类号： H01L21332
CPC分类号： H01L29/7813 , H01L29/04 , H01L29/045 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66348 , H01L29/66378 , H01L29/66659 , H01L29/66704 , H01L29/66734 , H01L29/66787 , H01L29/7393 , H01L29/7397 , H01L29/749 , H01L29/78 , H01L29/7803 , H01L29/7809 , H01L29/7816 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7828 , H01L29/7835
摘要： In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.
摘要翻译：在半导体器件中，p型基极区域设置在n型衬底中，从衬底的主表面沿垂直于主表面的方向延伸。 n +型源极区域在垂直方向上从主表面在p型基极区域中延伸，并且n +型漏极区域在p型基极区域中与p型基极区域分开延伸，漂移区域。形成沟槽，以在平行于主表面的方向上从n +型源极区域穿透p型基极区域。栅电极通过栅极绝缘膜形成在沟槽中。因此，当向栅电极施加电压时，可以在沟槽的深度方向上形成沟道区域。

8. 发明授权

US06525375B1 Semiconductor device having trench filled up with gate electrode 有权
标题翻译：具有填充有栅电极的沟槽的半导体器件
公开(公告)号：US06525375B1
公开(公告)日：2003-02-25
申请号：US09688154
申请日：2000-10-16
申请人： Hitoshi Yamaguchi , Toshio Sakakibara , Jun Sakakibara , Takumi Shibata , Toshiyuki Morishita
发明人： Hitoshi Yamaguchi , Toshio Sakakibara , Jun Sakakibara , Takumi Shibata , Toshiyuki Morishita
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/04 , H01L29/045 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66348 , H01L29/66378 , H01L29/66659 , H01L29/66704 , H01L29/66734 , H01L29/66787 , H01L29/7393 , H01L29/7397 , H01L29/749 , H01L29/78 , H01L29/7803 , H01L29/7809 , H01L29/7816 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7828 , H01L29/7835
摘要： In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.
摘要翻译：在半导体器件中，p型基极区域设置在n型衬底中，以从垂直于主表面的方向从衬底的主表面延伸。 n +型源极区域在垂直方向上从主表面延伸到p型基极区域中，并且n +型漏极区域在p型基极区域中与P型基极区域分开延伸，并且其间插入漂移区域。形成沟槽，以在平行于主表面的方向上从n +型源极区域穿透p型基极区域。栅电极通过栅极绝缘膜形成在沟槽中。因此，当向栅电极施加电压时，可以在沟槽的深度方向上形成沟道区域。

9. 发明申请

US20060261503A1 Process for producing dental prosthesis and kit for use for therein 审中-公开
标题翻译：用于生产牙科假体的工艺和用于其中的试剂盒
公开(公告)号：US20060261503A1
公开(公告)日：2006-11-23
申请号：US10563987
申请日：2004-07-13
申请人： Sumihito Sago , Toshio Sakakibara , Tatsuhiko Hirata , Atsushi Matsumoto
发明人： Sumihito Sago , Toshio Sakakibara , Tatsuhiko Hirata , Atsushi Matsumoto
IPC分类号： A61C13/00 , B05D3/00 , A61L33/00
CPC分类号： A61C13/081 , A61C5/70 , A61C5/77 , A61C13/0003 , A61C13/09 , A61C13/20
摘要： A method of manufacturing a dental prosthesis, including: (a) a step of preparing a substrate of the dental prosthesis that is constituted by a dental molding material; (b) a step of forming a back coating layer on at least a part of a surface of the substrate, by using a first porcelain that is constituted principally by ceramic; (c) a step of forming a casting mold such that the substrate is disposed in the casting mold and such that a void is provided on a surface of the back coating layer; and (d) a step of forming a cast coating layer on at least a part of a surface of the back coating layer, by pouring a second porcelain into the void at a casting temperature. The second porcelain is constituted principally by ceramic whose composition is different from that of the ceramic of the first porcelain that viscosity of the second porcelain at the casting temperature is lower than that of the first porcelain. Also disclosed are a kit and a dental porcelain set that are used for manufacturing the dental prosthesis.
摘要翻译：一种制造牙科假体的方法，包括：（a）制备由牙科模制材料构成的牙科假体的基底的步骤; （b）通过使用主要由陶瓷构成的第一瓷，在所述基材的表面的至少一部分上形成背涂层的步骤; （c）形成铸模，使得基板设置在铸模中，并且在背涂层的表面上设置空隙的步骤; 和（d）通过在铸造温度下将第二种陶瓷浇注到空隙中，在背涂层的表面的至少一部分上形成流延涂层的步骤。第二瓷主要由陶瓷构成，其组成与第一瓷的陶瓷不同，铸造温度下第二瓷的粘度低于第一瓷的粘度。还公开了用于制造牙科假体的试剂盒和牙科瓷器组。

10. 发明授权

US06770564B1 Method of etching metallic thin film on thin film resistor 失效
标题翻译：在薄膜电阻上蚀刻金属薄膜的方法
公开(公告)号：US06770564B1
公开(公告)日：2004-08-03
申请号：US09361980
申请日：1999-07-28
申请人： Ichiro Ito , Satoshi Shiraki , Tomio Yamamoto , Makoto Ohkawa , Atsumi Takahashi , Yasuaki Tsuzuki , Akito Fukui , Toshio Sakakibara , Takayuki Sugisaka
发明人： Ichiro Ito , Satoshi Shiraki , Tomio Yamamoto , Makoto Ohkawa , Atsumi Takahashi , Yasuaki Tsuzuki , Akito Fukui , Toshio Sakakibara , Takayuki Sugisaka
IPC分类号： H01L21302
CPC分类号： H01L28/24 , H01L21/32139
摘要： An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.
摘要翻译：在覆盖薄膜电阻器的阻挡金属上形成具有第一开口的Al膜。在Al膜和开口中形成光致抗蚀剂，并且被图案化以具有开口面积小于第一开口的开口面积并在第一开口中开口的第二开口，以暴露出阻挡金属。然后，通过第二开口蚀刻阻挡金属。由于阻挡金属从第一开口的开口端的内部蚀刻，因此防止了阻挡金属的切割。

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