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1. 发明申请

US20110153980A1 MULTI-STAGE RECONFIGURATION DEVICE AND RECONFIGURATION METHOD, LOGIC CIRCUIT CORRECTION DEVICE, AND RECONFIGURABLE MULTI-STAGE LOGIC CIRCUIT 失效
标题翻译：多阶段重新配置设备和重新配置方法，逻辑电路校正设备和可重新配置的多级逻辑电路
公开(公告)号：US20110153980A1
公开(公告)日：2011-06-23
申请号：US12294763
申请日：2007-03-02
申请人： Tsutomu Sasao , Kazuto Ishida
发明人： Tsutomu Sasao , Kazuto Ishida
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： H03K19/1733
摘要： To provide a device to reconfigure multi-level logic networks, which enable logic modification and reconfiguration of a multi-level logic network with small circuit area and low-power dissipation in a simple manner. For example, in the case of reconfiguring a multi-level logic network following logic modification for deleting an output vector F(b) of an objective logic function F(X) corresponding to an input vector b, unmodified pq elements are selected one by one from the nearest pq element EG to an output side. At this time, among output values of pq elements closer to an input side than selected pq elements, output values corresponding to the input vector, which equal an output value corresponding to any input variable X other than the input vector b are considered modified and thus not selected. Then, a selected output value corresponding to the input vector b is rewritten to an “invalid value”.
摘要翻译：提供一种重新配置多级逻辑网络的设备，其以简单的方式实现具有小电路面积和低功耗的多级逻辑网络的逻辑修改和重新配置。例如，在用于删除对应于输入向量b的对象逻辑函数F（X）的输出向量F（b）的逻辑修改之后重新配置多级逻辑网络的情况下，逐个选择未修改的pq元素从最近的pq元素EG到输出侧。此时，在比选择的pq元素更接近输入侧的pq元件的输出值之中，对应于与输入矢量b以外的任何输入变量X相对应的输出值的输入矢量的输出值被认为是修改的，因此未选中的。然后，将与输入向量b对应的选择的输出值重写为“无效值”。

2. 发明授权

US07486109B2 Programmable logic device 失效
标题翻译：可编程逻辑器件
公开(公告)号：US07486109B2
公开(公告)日：2009-02-03
申请号：US10551391
申请日：2004-03-31
申请人： Tsutomu Sasao , Yukihiro Iguchi
发明人： Tsutomu Sasao , Yukihiro Iguchi
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/1776 , H03K19/17728 , H03K19/17736 , H03K19/17784
摘要： The PLD that can change the number of input lines and the number of rail between the memories for logic according to the objective logic function, and to which the optimum design can be done to make the size of memory minimum. The memories for logic (4) are arranged in series, and LUT is memorized in them. The input variables are input from the external input lines to each memories for logic (4). The interconnection circuit (5) connects the output lines or the external input lines of memory for logic (4) in the preceding stage and the input lines of memory for logic (4) of the succeeding stage between two memories for logic (4), according to the information for connection memorized in memory for interconnections (6). By rewriting the information for connection according to the objective logic function, the interconnection circuit can be reconfigured, and the number of input lines and the number of rail can be changed. The size of memory can be suppressed to the minimum by optimizing the ratio of the number of rail and the number of input lines according to the logic function.
摘要翻译： PLD可以根据客观逻辑功能改变输入线路数量和逻辑存储器之间的轨道数量，并且可以进行最佳设计以使存储器的大小最小化。逻辑（4）的存储器被串联布置，并且LUT被存储在它们中。输入变量从外部输入线输入到逻辑（4）的每个存储器。互连电路（5）将用于逻辑（4）的两个存储器之间的逻辑（4）的输出线或存储器的外部输入线连接到后级逻辑（4）的存储器的输入线，根据存储在互连存储器（6）中的连接的信息。通过根据客观逻辑功能重写用于连接的信息，可以重新配置互连电路，并且可以改变输入线的数量和轨道的数量。通过根据逻辑功能优化轨道数和输入线数量的比例，可以将存储器的大小抑制到最小。

3. 发明申请

US20080204072A1 Programmable Logic Device 失效
公开(公告)号：US20080204072A1
公开(公告)日：2008-08-28
申请号：US10551391
申请日：2004-03-31
申请人： Tsutomu Sasao , Yukihiro Iguchi
发明人： Tsutomu Sasao , Yukihiro Iguchi
IPC分类号： G06F7/38
CPC分类号： H03K19/1776 , H03K19/17728 , H03K19/17736 , H03K19/17784
摘要： The invention relates to a connector (10) for connecting welding torch where the connector comprises a connector body (12) made of electrically insulating material, a cylindrical current transferring body (30) fitted on the cylindrical front part (13) of the connector body (12), made of electrically conductive material, where the current transferring body (30) has a threaded surface (32) and a side contact surface (35) besides the threaded surface (32) on its side surface, a threaded bore (37) on the side contact surface (35) for fixing current cable with screwed joint and a frontal contact surface (33), further an attachment bracket (60), made of electrically insulating plastic, the attachment bracket (60) has a sleeve part (62), which encircles space apart the threaded surface (32) and the sleeve part (62) has a flange (64) protruding from its front part for fixing, the flange (64) is provided with one or more holes (65) in it. The connector body (12) has a rear limiting surface (18) out of which a stem (75) projects, the stem (75) has a bore hole (77) in its centre line into which a liner (54) for wire guide is fixed, which liner leads in a nest (21) for fitting wire guide conduit end formed on the front surface (15) of the connector body (12), the current transferring body (30) has a pot-shape, having a bottom (39) in which there are openings (41, 42, 43) opening onto the nests (21, 23) formed on the front surface (15), further there is a positioning hole (27) in the side of the connector body (12) in the extension of the threaded bore (37) and the attachment bracket (60) has a conically narrowed part (68) projecting rearwards from the sleeve part (62), and on the inner surface near the end of the narrowed part (68) there is at least one screw thread (72) which The invention relates to a connector (10) for connecting welding torch where the connector comprises a connector body (12) made of electrically insulating material, a cylindrical current transferring body (30) fitted on the cylindrical front part (13) of the connector body (12), made of electrically conductive material, where the current transferring body (30) has a threaded surface (32) and a side contact surface (35) besides the threaded surface (32) on its side surface, a threaded bore (37) on the side contact surface (35) for fixing current cable with screwed joint and a frontal contact surface (33), further an attachment bracket (60), made of electrically insulating plastic, the attachment bracket (60) has a sleeve part (62), which encircled space apart the threaded surface (32) and the sleeve part (62) has a flange (64) protruding from its front part for fixing,—the flange (64) is provided with one or more holes (65) in it. The connector body (12) has a rear limiting surface (18) out of which a stem (75) projects, the stem (75) has a bore hole (77) in its centre line into which a liner (54) for wire guide is fixed, which liner leads in a nest (21) for fitting wire guide conduit end formed on the front surface (15) of the connector body (12), the current transferring body (30) has a pot-shape, having a bottom (39) in which there are openings (41, 42, 43) opening onto the nests (21, 23) formed on the front surface (15), fu

4. 发明授权

US08352677B2 Associative memory 有权
标题翻译：关联记忆
公开(公告)号：US08352677B2
公开(公告)日：2013-01-08
申请号：US12294786
申请日：2007-03-27
申请人： Tsutomu Sasao
发明人： Tsutomu Sasao
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： The associative memory comprises a simplified functional processing unit (SFPU), implemented by an LUT logic network, that implements simplified CAM function g, where g is the function derived from CAM function ƒ by replacing the value showing “invalid” with the don't care, an auxiliary memory that stores the inverse function ƒ−1 of said CAM function ƒ; and an output modifier that checks whether the output value of said SFPU is equal to the output value of the CAM function ƒ; wherein the SFPU produces the operational value (“tentative index value”) for the simplified CAM function g; the auxiliary memory produces the value of the inverse function ƒ−1 when the tentative index value is applied; the output modifier compares the input data with the value of the inverse function ƒ−1, and produces the output of said SFPU if they are the same, otherwise produces the signal showing the “invalid”.
摘要翻译：关联存储器包括由LUT逻辑网络实现的简化的功能处理单元（SFPU），其实现简化的CAM函数g，其中g是通过用无关的替换显示无效的值从CAM函数ƒ得到的函数，辅助存储器，其存储所述CAM功能ƒ的反函数ƒ-1; 以及输出修改器，其检查所述SFPU的输出值是否等于CAM功能的输出值; 其中SFPU产生简化CAM函数g的操作值（暂定索引值）; 当应用暂定索引值时，辅助存储器产生反函数ƒ-1的值; 输出修正器将输入数据与反函数ƒ-1的值进行比较，如果相同，则产生所述SFPU的输出，否则产生显示无效的信号。

5. 发明授权

US08285922B2 Address generator using LUT cascade logic network 有权
标题翻译：地址发生器使用LUT级联逻辑网络
公开(公告)号：US08285922B2
公开(公告)日：2012-10-09
申请号：US12294791
申请日：2007-03-27
申请人： Tsutomu Sasao
发明人： Tsutomu Sasao
IPC分类号： G06F12/02
CPC分类号： G06F17/30949 , G11C15/04 , Y02D10/45
摘要： The address generator has a hash network for producing hashed Y1, which is obtained by hushing X1, to an input vector X=(X1, X2), a tentative address generator Y1 for making an address generation function f(X) to a tentative address A′ when no hash collision occurs and otherwise making one of unique addresses A to A′, a data regenerator for producing X″=f−1(A′), a unique address generator for producing A′ when X″ coincides with X and otherwise producing “invalid value”, a complementary address generator for producing (X) to X, to which the unique address generator produces “invalid value”, and otherwise producing “invalid value”, and an output combiner which produces, when the outputs of the unique address generator and the complementary address generator have values other than the “invalid value”, the values as a unique address A and otherwise produces “invalid value” as A.
摘要翻译：地址生成器具有用于产生散列Y1的哈希网络，该哈希网络通过将X1缓冲获得到输入向量X =（X1，X2），用于将地址生成函数f（X）作为暂定地址的暂定地址生成器Y1 A'，当不发生哈希冲突而另外产生唯一地址A到A'时，用于产生X“= f-1（A'）的数据再生器，当X”与X一致时用于产生A'的唯一地址生成器否则产生无效值，用于产生（X）至X的互补地址发生器，唯一地址生成器产生无效值，否则产生无效值;以及输出组合器，当唯一地址发生器和互补地址生成器具有除无效值以外的值，该值作为唯一地址A，否则将无效值设为A.

6. 发明授权

US07844924B2 Device for reducing the width of graph and a method to reduce the width of graph, and a device for logic synthesis and a method for logic synthesis 失效
标题翻译：用于减小图形宽度的装置和减小图形宽度的方法，以及用于逻辑合成的装置和用于逻辑合成的方法
公开(公告)号：US07844924B2
公开(公告)日：2010-11-30
申请号：US10579743
申请日：2004-11-19
申请人： Tsutomu Sasao , Yukihiro Iguchi
发明人： Tsutomu Sasao , Yukihiro Iguchi
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5054
摘要： A device for logic synthesis that can be used to synthesize LUT logic circuit having intermediate outputs for multiple-output logic functions. The device includes means to store node table 8 storing Binary Decision Diagram for Characteristic Function (BDD_for_CF) of the characteristic function χ(X, Y) of the multiple-output logic function f(X), means to store LUTs 16, means to reduce by shorting 11 partitioning BDD_for_CF into the subgraphs B0 and B1 at the partition line in the height lev of the partition and executing shorten-processing, means to measure the width W of BDDs 12 calculating the width W at the partition line, means to compute the intermediate variables 13 calculating the number of the intermediate variables u according to the width W, means to generate an LUT 14 generating the LUT for the sub-graph B0, and means to reconstruct BDDs 15 generating a binary tree that has the same number of control inputs as that of the intermediate variables u, replacing the sub-graph B0 with the binary tree and reconstructing the BDD_for_CF.
摘要翻译：用于逻辑合成的装置，其可用于合成具有用于多输出逻辑功能的中间输出的LUT逻辑电路。该装置包括存储存储多输出逻辑函数f（X）的特征函数χ（X，Y）的特征函数二进制判定图（BDD_for_CF）的节点表8的装置，存储LUT16的装置，减少通过将分区BDD_for_CF 11分割成分区的高度lev的分割线上的子图B0和B1，并执行缩短处理，测量计算分区线宽度W的BDD12的宽度W的装置，根据宽度W计算中间变量u的数量的中间变量13意味着生成生成用于子图B0的LUT的LUT 14，以及重构BDD 15的装置，生成具有相同数量的控制的二叉树输入与中间变量u的输入，用二叉树替换子图B0并重建BDD_for_CF。

7. 发明申请

US20100228911A1 ASSOCIATED MEMORY 有权
标题翻译：相关记忆
公开(公告)号：US20100228911A1
公开(公告)日：2010-09-09
申请号：US12294786
申请日：2007-03-27
申请人： Tsutomu Sasao
发明人： Tsutomu Sasao
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： The associative memory comprises a simplified functional processing unit (SFPU), implemented by an LUT logic network, that implements simplified CAM function g, where g is the function derived from CAM function ƒ by replacing the value showing “invalid” with the don't care, an auxiliary memory that stores the inverse function ƒ−1 of said CAM function ƒ; and an output modifier that checks whether the output value of said SFPU is equal to the output value of the CAM function ƒ; wherein the SFPU produces the operational value (“tentative index value”) for the simplified CAM function g; the auxiliary memory produces the value of the inverse function ƒ−1 when the tentative index value is applied; the output modifier compares the input data with the value of the inverse function ƒ−1, and produces the output of said SFPU if they are the same, otherwise produces the signal showing the “invalid”.
摘要翻译：关联存储器包括由LUT逻辑网络实现的简化功能处理单元（SFPU），其实现简化的CAM函数g，其中g是从CAM函数ƒ得到的函数，通过用不要替换显示“无效”的值关心，存储所述CAM功能的反函数ƒ-1的辅助存储器; 以及输出修改器，其检查所述SFPU的输出值是否等于CAM功能的输出值; 其中SFPU产生简化CAM函数g的操作值（“暂定索引值”）; 当应用暂定索引值时，辅助存储器产生反函数ƒ-1的值; 输出修正器将输入数据与反函数ƒ-1的值进行比较，如果相同，则产生所述SFPU的输出，否则产生显示“无效”的信号。

8. 发明授权

US08719549B2 Device to reconfigure multi-level logic networks, method to reconfigure multi-level logic networks, device to modify logic networks, and reconfigurable multi-level logic network 失效
标题翻译：重新配置多级逻辑网络的设备，重新配置多级逻辑网络的方法，修改逻辑网络的设备和可重配置的多级逻辑网络
公开(公告)号：US08719549B2
公开(公告)日：2014-05-06
申请号：US12294763
申请日：2007-03-02
申请人： Tsutomu Sasao
发明人： Tsutomu Sasao
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： H03K19/1733
摘要： To provide a device to reconfigure multi-level logic networks, which enable logic modification and reconfiguration of a multi-level logic network with small circuit area and low-power dissipation in a simple manner. For example, in the case of reconfiguring a multi-level logic network following logic modification for deleting an output vector F(b) of an objective logic function F(X) corresponding to an input vector b, unmodified pq elements are selected one by one from the nearest pq element EG to an output side. At this time, among output values of pq elements closer to an input side than selected pq elements, output values corresponding to the input vector, which equal an output value corresponding to any input variable X other than the input vector b are considered modified and thus not selected. Then, a selected output value corresponding to the input vector b is rewritten to an “invalid value”.
摘要翻译：提供一种重新配置多级逻辑网络的设备，其以简单的方式实现具有小电路面积和低功耗的多级逻辑网络的逻辑修改和重新配置。例如，在用于删除对应于输入向量b的对象逻辑函数F（X）的输出向量F（b）的逻辑修改之后重新配置多级逻辑网络的情况下，逐个选择未修改的pq元素从最近的pq元素EG到输出侧。此时，在比选择的pq元素更接近输入侧的pq元件的输出值之中，对应于与输入矢量b以外的任何输入变量X相对应的输出值的输入矢量的输出值被认为是修改的，因此未选中的。然后，将与输入向量b对应的选择的输出值重写为“无效值”。

9. 发明申请

US20100228947A1 ADDRESS GENERATOR 有权
标题翻译：地址发生器
公开(公告)号：US20100228947A1
公开(公告)日：2010-09-09
申请号：US12294791
申请日：2007-03-27
申请人： Tsutomu Sasao
发明人： Tsutomu Sasao
IPC分类号： G06F12/06
CPC分类号： G06F17/30949 , G11C15/04 , Y02D10/45
摘要： The address generator has a hash network for producing hashed Y1, which is obtained by hushing X1, to an input vector X=(X1, X2), a tentative address generator Y1 for making an address generation function f(X) to a tentative address A′ when no hash collision occurs and otherwise making one of unique addresses A to A′, a data regenerator for producing X″=f−1(A′), a unique address generator for producing A′ when X″ coincides with X and otherwise producing “invalid value”, a complementary address generator for producing (X) to X, to which the unique address generator produces “invalid value”, and otherwise producing “invalid value”, and an output combiner which produces, when the outputs of the unique address generator and the complementary address generator have values other than the “invalid value”, the values as a unique address A and otherwise produces “invalid value” as A.
摘要翻译：地址生成器具有用于产生散列Y1的哈希网络，该哈希网络通过将X1缓冲获得到输入向量X =（X1，X2），用于将地址生成函数f（X）作为暂定地址的暂定地址生成器Y1 A'，当不发生哈希冲突而另外产生唯一地址A到A'时，用于产生X“= f-1（A'）的数据再生器，当X”与X一致时用于产生A'的唯一地址生成器否则产生“无效值”，用于产生（X）至X的互补地址发生器，唯一地址发生器产生“无效值”，否则产生“无效值”，以及输出组合器，当输出唯一地址生成器和互补地址生成器具有除“无效值”之外的值，该值作为唯一地址A，否则将产生“无效值”为A.

10. 发明申请

US20070174804A1 Device for reducing the width of graph and a method to reduce the width of graph, and a device for logic synthesis and a method for logic synthesis 失效
标题翻译：用于减小图形宽度的装置和减小图形宽度的方法，以及用于逻辑合成的装置和用于逻辑合成的方法
公开(公告)号：US20070174804A1
公开(公告)日：2007-07-26
申请号：US10579743
申请日：2004-11-19
申请人： Tsutomu Sasao , Yukihiro Iguchi
发明人： Tsutomu Sasao , Yukihiro Iguchi
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： The object of the present invention is to present a device for logic synthesis that can be used to synthesize LUT logic circuit having intermediate outputs for multiple-output logic functions. The device for logic synthesis comprises: means to store node table 8 storing Binary Decision Diagram for Characteristic Function (BDD_for_CF) of the characteristic function χ(X, Y) of the multiple-output logic function f(X), means to store LUTs 16, means to reduce by shorting 11 partitioning BDD_for_CF into the subgraphs B0 and B1 at the partition line in the height lev of the partition and executing shorten-processing, means to measure the width W of BDDs 12 calculating the width W at the partition line, means to compute the intermediate variables 13 calculating the number of the intermediate variables u according to the width W, means to generate an LUT 14 generating the LUT for the sub-graph B0, and means to reconstruct BDDs 15 generating a binary tree that has the same number of control inputs as that of the intermediate variables u, replacing the sub-graph B0 with the binary tree and reconstructing the BDD_for_CF.
摘要翻译：本发明的目的是提出一种用于逻辑合成的装置，其可用于合成具有用于多输出逻辑功能的中间输出的LUT逻辑电路。用于逻辑合成的装置包括：存储存储多输出逻辑函数f（X）的特征函数chi（X，Y）的特征函数的二进制判定图（BDD_for_CF）的节点表8的装置，用于存储LUT16 意味着通过将分区BDD_for_CF 11分割成分区的高度lev中的分区线上的子图B 0和B 1来减少，并执行缩短处理，意味着测量计算分割线宽度W的BDD12的宽度W，计算根据宽度W计算中间变量u的数量的中间变量13的装置，生成生成用于子带的LUT的LUT 14的装置，图形B 0 ，并且用于重建BDD 15的装置，其生成具有与中间变量u相同数量的控制输入的二进制树，替换子图B 0 与二进制树并重建BDD_for_CF。

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