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1. 发明授权

US09245746B2 Semiconductor composite film with heterojunction and manufacturing method thereof 有权
标题翻译：具有异质结的半导体复合膜及其制造方法
公开(公告)号：US09245746B2
公开(公告)日：2016-01-26
申请号：US14048971
申请日：2013-10-08
申请人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
发明人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L29/66 , H01L21/02 , H01L29/78 , H01L29/12
CPC分类号： H01L29/205 , H01L21/02378 , H01L21/0242 , H01L21/0254 , H01L21/02664 , H01L21/30612 , H01L29/12 , H01L29/2003 , H01L29/7845 , H01L29/7849
摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
摘要翻译：本发明公开了一种具有异质结的半导体复合膜及其制造方法。半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。该凹槽用于减轻半导体复合膜中的应变。

2. 发明授权

US09105757B2 Junction barrier Schottky diode and manufacturing method thereof 有权
标题翻译：交联势垒肖特基二极管及其制造方法
公开(公告)号：US09105757B2
公开(公告)日：2015-08-11
申请号：US14040670
申请日：2013-09-28
申请人： Chih-Fang Huang , Tsung-Yi Huang , Chien-Wei Chiu , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Chieh Hsiao , Ya-Hsien Liu , Po-Chin Peng
发明人： Chih-Fang Huang , Tsung-Yi Huang , Chien-Wei Chiu , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Chieh Hsiao , Ya-Hsien Liu , Po-Chin Peng
IPC分类号： H01L29/872 , H01L29/66 , H01L29/868 , H01L29/06 , H01L29/20 , H01L29/205
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/66212
摘要： The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.
摘要翻译：本发明公开了一种接合势垒肖特基（JBS）二极管及其制造方法。 JBS二极管包括：N型氮化镓（GaN）衬底; 形成在N型GaN衬底上的氮化镓铝（AlGaN）阻挡层; 在N型GaN衬底上形成的P型氮化镓（GaN）层; 至少部分地形成在AlGaN阻挡层上的阳极导电层，其中在所述阳极导电层的一部分和所述AlGaN阻挡层之间形成肖特基接触; 以及阴极导电层，其形成在N型GaN衬底上，其中在阴极导电层和N型GaN衬底之间形成欧姆接触，并且阴极导电层不直接连接到阳极导电层。

3. 发明申请

US20130299840A1 SCHOTTKY BARRIER DIODE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：肖特彼勒二极管及其制造方法
公开(公告)号：US20130299840A1
公开(公告)日：2013-11-14
申请号：US13466550
申请日：2012-05-08
申请人： Chieh-Hsiung Kuan , Ting-Wei Liao , Chien-Wei Chiu , Tsung-Yi Huang
发明人： Chieh-Hsiung Kuan , Ting-Wei Liao , Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L29/20 , H01L21/28 , H01L29/872
CPC分类号： H01L29/417 , H01L29/2003 , H01L29/413 , H01L29/66212 , H01L29/872
摘要： The present invention discloses a Schottky barrier diode (SBD) and a manufacturing method thereof. The SBD includes: a semiconductor layer, which has multiple openings forming an opening array; and an anode, which has multiple conductive protrusions protruding into the multiple openings and forming a conductive array; wherein a Schottky contact is formed between the semiconductor layer and the anode.
摘要翻译：本发明公开了一种肖特基势垒二极管（SBD）及其制造方法。 SBD包括：半导体层，其具有形成开口阵列的多个开口; 以及阳极，其具有突出到所述多个开口中并形成导电阵列的多个导电突起; 其中在所述半导体层和所述阳极之间形成肖特基接触。

4. 发明授权

US09590049B2 Semiconductor composite film with heterojunction and manufacturing method thereof 有权
标题翻译：具有异质结的半导体复合膜及其制造方法
公开(公告)号：US09590049B2
公开(公告)日：2017-03-07
申请号：US14966818
申请日：2015-12-11
申请人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
发明人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L21/336 , H01L29/205 , H01L29/78 , H01L21/02 , H01L21/306 , H01L29/20 , H01L29/12
CPC分类号： H01L29/205 , H01L21/02378 , H01L21/0242 , H01L21/0254 , H01L21/02664 , H01L21/30612 , H01L29/12 , H01L29/2003 , H01L29/7845 , H01L29/7849
摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
摘要翻译：本发明公开了一种具有异质结的半导体复合膜及其制造方法。半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。该凹槽用于减轻半导体复合膜中的应变。

5. 发明申请

US20160099320A1 SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有异质性的半导体复合膜及其制造方法
公开(公告)号：US20160099320A1
公开(公告)日：2016-04-07
申请号：US14966818
申请日：2015-12-11
申请人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
发明人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L29/205 , H01L21/02 , H01L21/306 , H01L29/20
CPC分类号： H01L29/205 , H01L21/02378 , H01L21/0242 , H01L21/0254 , H01L21/02664 , H01L21/30612 , H01L29/12 , H01L29/2003 , H01L29/7845 , H01L29/7849
摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
摘要翻译：本发明公开了一种具有异质结的半导体复合膜及其制造方法。半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。该凹槽用于减轻半导体复合膜中的应变。

6. 发明申请

US20150021615A1 JUNCTION BARRIER SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：接线棒肖特基二极管及其制造方法
公开(公告)号：US20150021615A1
公开(公告)日：2015-01-22
申请号：US14040670
申请日：2013-09-28
申请人： Chih-Fang Huang , Tsung-Yi Huang , Chien-Wei Chiu , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Chieh Hsiao , Ya-Hsien Liu , Po-Chin Peng
发明人： Chih-Fang Huang , Tsung-Yi Huang , Chien-Wei Chiu , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Chieh Hsiao , Ya-Hsien Liu , Po-Chin Peng
IPC分类号： H01L29/872 , H01L29/66 , H01L29/868
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/66212
摘要： The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.
摘要翻译：本发明公开了一种接合势垒肖特基（JBS）二极管及其制造方法。 JBS二极管包括：N型氮化镓（GaN）衬底; 形成在N型GaN衬底上的氮化镓铝（AlGaN）阻挡层; 在N型GaN衬底上形成的P型氮化镓（GaN）层; 至少部分地形成在AlGaN阻挡层上的阳极导电层，其中在所述阳极导电层的一部分和所述AlGaN阻挡层之间形成肖特基接触; 以及阴极导电层，其形成在N型GaN衬底上，其中在阴极导电层和N型GaN衬底之间形成欧姆接触，并且阴极导电层不直接连接到阳极导电层。

7. 发明申请

US20140179079A1 MANUFACTURING METHOD OF LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：侧向双金属氧化物半导体器件的制造方法
公开(公告)号：US20140179079A1
公开(公告)日：2014-06-26
申请号：US14044626
申请日：2013-10-02
申请人： Tsung-Yi Huang , Chien-Wei Chiu
发明人： Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/66
CPC分类号： H01L29/66681 , H01L29/0607 , H01L29/0619 , H01L29/0634 , H01L29/42368 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a manufacturing method of a lateral double diffused metal oxide semiconductor (LDMOS) device. The LDMOS device includes: a substrate, an epitaxial layer, a first conductivity type channel stop region, a first conductivity type top region, an isolation oxide region, a field oxide region, a first conductivity type well, a gate, a second conductivity type lightly doped region, a second conductivity type source, and a second conductivity type drain. The present invention defines the channel stop region, the top region, the isolation oxide region, and the field oxide region by a same oxide region mask, wherein the isolation oxide region and the field oxide region are located on the channel stop region and the top region respectively.
摘要翻译：本发明公开了一种横向双扩散金属氧化物半导体（LDMOS）器件的制造方法。 LDMOS器件包括：衬底，外延层，第一导电类型沟道阻挡区，第一导电类型顶区，隔离氧化物区，场氧化物区，第一导电型阱，栅极，第二导电类型轻掺杂区域，第二导电型源极和第二导电类型漏极。本发明通过相同的氧化物区掩模限定了通道阻挡区域，顶部区域，隔离氧化物区域和场氧化物区域，其中隔离氧化物区域和场氧化物区域位于通道停止区域和顶部区域。

8. 发明申请

US20140061786A1 Double Diffused Metal Oxide Semiconductor Device and Manufacturing Method Thereof 审中-公开
标题翻译：双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US20140061786A1
公开(公告)日：2014-03-06
申请号：US13603385
申请日：2012-09-04
申请人： Tsung-Yi Huang , Chien-Wei Chiu
发明人： Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66681 , H01L29/063 , H01L29/0696 , H01L29/1083 , H01L29/42368 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes a first conductive type substrate, a second conductive type high voltage well, a first conductive type deep buried region, a field oxide region, a first conductive type body region, a gate, a second conductive type source, and a second conductive type drain. The deep buried region is formed below the high voltage well with a gap in between, and the gap is not less than a predetermined distance.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括第一导电型衬底，第二导电型高电压阱，第一导电类型深埋入区域，场氧化物区域，第一导电类型体区域，栅极，第二导电型源极和第二导电类型源极导电型漏极。深埋区域形成在高压井的下方，间隙为间隙，间隙不小于预定距离。

9. 发明申请

US20130207185A1 ISOLATED DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：隔离装置及其制造方法
公开(公告)号：US20130207185A1
公开(公告)日：2013-08-15
申请号：US13370691
申请日：2012-02-10
申请人： Tsung-Yi Huang , Chien-Wei Chiu
发明人： Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/086 , H01L29/0611 , H01L29/0615 , H01L29/0619 , H01L29/0847 , H01L29/1083 , H01L29/66492 , H01L29/66659 , H01L29/7835
摘要： An isolated device is formed in a substrate in which is formed a high voltage device. The isolated device includes: an isolated well formed in the substrate by a lithography process and an ion implantation process used in forming the high voltage device; a gate formed on the substrate; a source and a drain, which are located in the isolated well at both sides of the gate respectively; a drift-drain region formed beneath the substrate surface, wherein the gate and the drain are separated by the drift-drain region, and the drain is in the drift-drain region; and a mitigation region, which is formed in the substrate and has a shallowest portion located at least below 90% of a depth of the drift-drain region as measured from the substrate surface, wherein the mitigation region and the drift-drain region are defined by a same lithography process.
摘要翻译：隔离器件形成在形成高电压器件的衬底中。隔离装置包括：通过光刻工艺在衬底中形成的隔离阱和用于形成高压器件的离子注入工艺; 形成在基板上的栅极; 源极和漏极分别位于门的两侧的隔离井中; 形成在所述衬底表面下方的漂移漏极区，其中所述栅极和所述漏极由所述漂移 - 漏极区分离，并且所述漏极在所述漂移 - 漏极区中; 以及缓解区域，其形成在所述衬底中，并且具有位于所述衬底表面测量的至少位于所述漂移 - 漏极区域的深度的90％以下的最浅部分，其中所述缓解区域和所述漂移 - 漏极区域被限定通过相同的光刻工艺。

10. 发明授权

US09362381B2 Insulated gate bipolar transistor with a lateral gate structure and gallium nitride substrate and manufacturing method thereof 有权
标题翻译：具有横向栅极结构和氮化镓衬底的绝缘栅双极晶体管及其制造方法
公开(公告)号：US09362381B2
公开(公告)日：2016-06-07
申请号：US14971496
申请日：2015-12-16
申请人： Chih-Fang Huang , Tsung-Yi Huang , Chien-Wei Chiu , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Chieh Hsiao , Ya-Hsien Liu , Po-Chin Peng
发明人： Chih-Fang Huang , Tsung-Yi Huang , Chien-Wei Chiu , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Chieh Hsiao , Ya-Hsien Liu , Po-Chin Peng
IPC分类号： H01L29/66 , H01L29/73 , H01L29/10 , H01L29/20 , H01L29/201 , H01L27/07
CPC分类号： H01L29/66325 , H01L27/0722 , H01L29/1095 , H01L29/2003 , H01L29/201 , H01L29/42316 , H01L29/66462 , H01L29/7787
摘要： The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.
摘要翻译：本发明公开了一种绝缘栅双极晶体管（IGBT）及其制造方法。 IGBT包括：氮化镓（GaN）衬底，具有第一导电类型的第一GaN层，具有第一导电类型的第二GaN层，具有第二导电类型或本征导电类型的第三GaN层，以及栅极形成在GaN衬底上。第一GaN层形成在GaN衬底上并且具有垂直于GaN衬底的侧壁。第二GaN层形成在GaN衬底上，并通过栅极与第一GaN层分离。第三GaN层形成在第一GaN层上，并通过第一GaN层与GaN衬底分离。门具有在横向方向上与侧壁相邻的侧板以控制通道。

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