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1. 发明授权

US08538017B2 Encryption device 有权
标题翻译：加密设备
公开(公告)号：US08538017B2
公开(公告)日：2013-09-17
申请号：US13192122
申请日：2011-07-27
申请人： Tsukasa Endo , Hideo Shimizu , Yuichi Komano , Hanae Ikeda , Atsushi Shimbo
发明人： Tsukasa Endo , Hideo Shimizu , Yuichi Komano , Hanae Ikeda , Atsushi Shimbo
IPC分类号： H04L9/00
CPC分类号： H04L9/003 , H04L9/0631 , H04L2209/046 , H04L2209/24
摘要： According to one embodiment, in an encryption device, a segmentation unit segments masked plain data into pieces of first segmented data. A first processing unit generates pieces of second segmented data from the pieces of first segmented data. A nonlinear transform unit generates pieces of third segmented data transformed from the pieces of second segmented data. A data integration unit integrates fourth segmented data to generate masked encrypted data. An unmask processing unit generates encrypted data from the masked encrypted data. The exclusive OR of the pieces of second segmented data matches the exclusive OR of input data, subjected to nonlinear transform processing and calculated from the plain data, and the first mask. The exclusive OR of the pieces of third segmented data matches the exclusive OR of transform data, obtained when the nonlinear transform processing is performed on the input data, and the second mask.
摘要翻译：根据一个实施例，在加密设备中，分割单元将屏蔽的普通数据分割成多个第一分段数据。第一处理单元从第一分段数据生成第二分段数据。非线性变换单元生成从第二分割数据变换的第三分段数据。数据集成单元集成第四分段数据以生成被掩蔽的加密数据。解密处理单元从掩蔽的加密数据生成加密数据。第二分段数据的异或与进行非线性变换处理并从普通数据计算的输入数据的异或与第一掩码相匹配。第三分段数据的异或与对输入数据执行非线性变换处理时获得的变换数据的异或与第二掩码相匹配。

2. 发明申请

US20120069998A1 ENCRYPTION DEVICE 有权
标题翻译：加密设备
公开(公告)号：US20120069998A1
公开(公告)日：2012-03-22
申请号：US13192122
申请日：2011-07-27
申请人： Tsukasa ENDO , Hideo Shimizu , Yuichi Komano , Hanae Ikeda , Atsushi Shimbo
发明人： Tsukasa ENDO , Hideo Shimizu , Yuichi Komano , Hanae Ikeda , Atsushi Shimbo
IPC分类号： H04L9/00
CPC分类号： H04L9/003 , H04L9/0631 , H04L2209/046 , H04L2209/24
摘要： According to one embodiment, in an encryption device, a segmentation unit segments masked plain data into pieces of first segmented data. A first processing unit generates pieces of second segmented data from the pieces of first segmented data. A nonlinear transform unit generates pieces of third segmented data transformed from the pieces of second segmented data. A data integration unit integrates fourth segmented data to generate masked encrypted data. An unmask processing unit generates encrypted data from the masked encrypted data. The exclusive OR of the pieces of second segmented data matches the exclusive OR of input data, subjected to nonlinear transform processing and calculated from the plain data, and the first mask. The exclusive OR of the pieces of third segmented data matches the exclusive OR of transform data, obtained when the nonlinear transform processing is performed on the input data, and the second mask.
摘要翻译：根据一个实施例，在加密设备中，分割单元将屏蔽的普通数据分割成多个第一分段数据。第一处理单元从第一分段数据生成第二分段数据。非线性变换单元生成从第二分割数据变换的第三分段数据。数据集成单元集成第四分段数据以生成被掩蔽的加密数据。解密处理单元从掩蔽的加密数据生成加密数据。第二分段数据的异或与进行非线性变换处理并从普通数据计算的输入数据的异或与第一掩码相匹配。第三分段数据的异或与对输入数据执行非线性变换处理时获得的变换数据的异或与第二掩码相匹配。

3. 发明申请

US20120307997A1 ENCRYPTION DEVICE 有权
标题翻译：加密设备
公开(公告)号：US20120307997A1
公开(公告)日：2012-12-06
申请号：US13585391
申请日：2012-08-14
申请人： Tsukasa Endo , Yuichi Komano , Koichi Fujisaki , Hideo Shimizu , Hanae Ikeda , Atsushi Shimbo
发明人： Tsukasa Endo , Yuichi Komano , Koichi Fujisaki , Hideo Shimizu , Hanae Ikeda , Atsushi Shimbo
IPC分类号： H04L9/28
CPC分类号： H04L9/0631 , H04L9/003
摘要： According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N−1.
摘要翻译：根据实施例，加密装置使用加密密钥进行加密处理，并从普通数据计算加密数据。加密装置包括：寄存器; 输入单元，被配置为接收普通数据; 第一部分加密单元，被配置为从所述普通数据计算第一中间数据; 第二部分加密单元，被配置为基于第i个中间数据和加密密钥计算第（i + 1）个中间数据; 第一变换单元，被配置为：将第j个中间数据变换为第j变换数据; 并将第j个变换数据存储在寄存器中; 以及第二变换单元，被配置为将第j个变换后的数据变换为第j个中间数据; 第三部分加密单元，被配置为从第N个中间数据计算加密数据。第二部分加密单元被配置为重复处理以计算（j + 1）中间数据，而j等于从1到N-1。

4. 发明授权

US09288040B2 Encryption device 有权
标题翻译：加密设备
公开(公告)号：US09288040B2
公开(公告)日：2016-03-15
申请号：US13585391
申请日：2012-08-14
申请人： Tsukasa Endo , Yuichi Komano , Koichi Fujisaki , Hideo Shimizu , Hanae Ikeda , Atsushi Shimbo
发明人： Tsukasa Endo , Yuichi Komano , Koichi Fujisaki , Hideo Shimizu , Hanae Ikeda , Atsushi Shimbo
IPC分类号： H04L9/06 , H04L9/00
CPC分类号： H04L9/0631 , H04L9/003
摘要： According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N−1.
摘要翻译：根据实施例，加密装置使用加密密钥进行加密处理，并从普通数据计算加密数据。加密装置包括：寄存器; 输入单元，被配置为接收普通数据; 第一部分加密单元，被配置为从所述普通数据计算第一中间数据; 第二部分加密单元，被配置为基于第i个中间数据和加密密钥计算第（i + 1）个中间数据; 第一变换单元，被配置为：将第j个中间数据变换为第j变换数据; 并将第j个变换数据存储在寄存器中; 以及第二变换单元，被配置为将第j个变换后的数据变换为第j个中间数据; 第三部分加密单元，被配置为从第N个中间数据计算加密数据。第二部分加密单元被配置为重复处理以计算（j + 1）中间数据，而j等于从1到N-1。

5. 发明授权

US08401180B2 Non-linear data converter, encoder and decoder 有权
标题翻译：非线性数据转换器，编码器和解码器
公开(公告)号：US08401180B2
公开(公告)日：2013-03-19
申请号：US12053143
申请日：2008-03-21
申请人： Yuichi Komano , Hideo Shimizu , Koichi Fujisaki , Hideyuki Miyake , Atsushi Shimbo
发明人： Yuichi Komano , Hideo Shimizu , Koichi Fujisaki , Hideyuki Miyake , Atsushi Shimbo
IPC分类号： H04K1/00
CPC分类号： H04L9/0618 , H04L9/003 , H04L2209/046 , H04L2209/08 , H04L2209/24
摘要： According to an aspect of the present invention, there is provided a non-linear data converter including: first to fourth converters that each performs a respective converting process on an input bit string to output respective output bit string; a generator that generates a random number bit string; and a selector that selects any one of the output bit strings from the first to fourth converters based on the random number bit string. Each of the converting processes is equivalent to performing a first mask process, a non-linear conversion predetermined for an encoding or a decoding and a second mask process.
摘要翻译：根据本发明的一个方面，提供了一种非线性数据转换器，包括：第一至第四转换器，其对输入的比特串执行相应的转换处理，以输出相应的输出比特串; 产生随机数位串的发生器; 以及选择器，其基于随机数位串来选择来自第一至第四转换器的输出位串中的任何一个。每个转换处理等效于执行第一掩码处理，为编码或解码预定的非线性转换和第二掩码处理。

6. 发明申请

US20080292100A1 NON-LINEAR DATA CONVERTER, ENCODER AND DECODER 有权
标题翻译：非线性数据转换器，编码器和解码器
公开(公告)号：US20080292100A1
公开(公告)日：2008-11-27
申请号：US12053143
申请日：2008-03-21
申请人： Yuichi KOMANO , Hideo Shimizu , Koichi Fujisaki , Hideyuki Miyake , Atsushi Shimbo
发明人： Yuichi KOMANO , Hideo Shimizu , Koichi Fujisaki , Hideyuki Miyake , Atsushi Shimbo
IPC分类号： H04L9/06
CPC分类号： H04L9/0618 , H04L9/003 , H04L2209/046 , H04L2209/08 , H04L2209/24
摘要： According to an aspect of the present invention, there is provided a non-linear data converter including: first to fourth converters that each performs a respective converting process on an input bit string to output respective output bit string; a generator that generates a random number bit string; and a selector that selects any one of the output bit strings from the first to fourth converters based on the random number bit string. Each of the converting processes is equivalent to performing a first mask process, a non-linear conversion predetermined for an encoding or a decoding and a second mask process.
摘要翻译：根据本发明的一个方面，提供了一种非线性数据转换器，包括：第一至第四转换器，其对输入的比特串执行相应的转换处理，以输出相应的输出比特串; 产生随机数位串的发生器; 以及选择器，其基于随机数位串来选择来自第一至第四转换器的输出位串中的任何一个。每个转换处理等效于执行第一掩码处理，为编码或解码预定的非线性转换和第二掩码处理。

7. 发明申请

US20070140478A1 Encryption apparatus and encryption method 审中-公开
标题翻译：加密设备和加密方法
公开(公告)号：US20070140478A1
公开(公告)日：2007-06-21
申请号：US11523609
申请日：2006-09-20
申请人： Yuichi Komano , Hideo Shimizu , Atsushi Shimbo
发明人： Yuichi Komano , Hideo Shimizu , Atsushi Shimbo
IPC分类号： H04L9/28
CPC分类号： H04L9/0618 , H04L9/003 , H04L2209/046 , H04L2209/08
摘要： An encryption apparatus for generating a ciphertext block from a plaintext block is disclosed. A selector selects at random one mask random number from a plurality of random numbers generated by a random number generator. A mask processing unit executes mask processing of a plaintext block by using the mask random number selected by the selector. A storage unit stores a first table representing an initial S-box. A converter converts the first table into a second table representing a deformed S-box on the basis of the mask random number selected by the selector. An encryption unit generates a ciphertext block by shuffling the mask-processed plaintext block using the second table.
摘要翻译：公开了一种用于从明文块生成密文块的加密装置。选择器从随机数发生器产生的多个随机数中随机选择一个掩码随机数。掩模处理单元通过使用由选择器选择的掩码随机数执行明文块的掩码处理。存储单元存储表示初始S盒的第一表。 A转换器基于由选择器选择的掩码随机数将第一表转换成表示变形的S盒的第二表。加密单元通过使用第二表来混洗经过掩模处理的明文块来生成密文块。

8. 发明授权

US08909689B2 Arithmetic device 有权
标题翻译：算术设备
公开(公告)号：US08909689B2
公开(公告)日：2014-12-09
申请号：US13361074
申请日：2012-01-30
申请人： Hideo Shimizu , Yuichi Komano , Koichi Fujisaki , Shinichi Kawamura
发明人： Hideo Shimizu , Yuichi Komano , Koichi Fujisaki , Shinichi Kawamura
IPC分类号： G06F7/72
CPC分类号： G06F7/728
摘要： According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.
摘要翻译：根据一个实施例，第一移位量计算单元从蒙哥马利乘积结果z的计算的中间结果的较低有效位向更高有效位对连续零的数进行计数，并计算第一移位量。第二移位量计算单元将来自冗余二进制表示的整数x的较低有效位朝向更高有效位的连续零的数目计数，并计算第二移位量。加法/减法单元相对于已被移位了第一移位量的中间结果，整数p和已被位移第二移位的整数y加/减来计算中间结果量。当第一移位量的和等于整数p的位数时，输出单元输出作为蒙哥马利乘数结果z的中间结果。

9. 发明申请

US20120131078A1 ARITHMETIC DEVICE 有权
标题翻译：算术设备
公开(公告)号：US20120131078A1
公开(公告)日：2012-05-24
申请号：US13361074
申请日：2012-01-30
申请人： Hideo Shimizu , Yuichi Komano , Koichi Fujisaki , Shinichi Kawamura
发明人： Hideo Shimizu , Yuichi Komano , Koichi Fujisaki , Shinichi Kawamura
IPC分类号： G06F7/523 , G06F7/50 , G06F5/01 , G06F7/48
CPC分类号： G06F7/728
摘要： According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.
摘要翻译：根据一个实施例，第一移位量计算单元从蒙哥马利乘积结果z的计算的中间结果的较低有效位向更高有效位对连续零的数进行计数，并计算第一移位量。第二移位量计算单元将来自冗余二进制表示的整数x的较低有效位朝向更高有效位的连续零的数目计数，并计算第二移位量。加法/减法单元相对于已被移位了第一移位量的中间结果，整数p和已被位移第二移位的整数y加/减来计算中间结果量。当第一移位量的和等于整数p的位数时，输出单元输出作为蒙哥马利乘数结果z的中间结果。

10. 发明申请

US20090024887A1 SEMICONDUCTOR STORAGE DEVICE, DATA WRITE METHOD AND DATA READ METHOD 审中-公开
标题翻译：半导体存储器件，数据写入方法和数据读取方法
公开(公告)号：US20090024887A1
公开(公告)日：2009-01-22
申请号：US12032877
申请日：2008-02-18
申请人： Daijiro Kimbara , Hiroo Nakano , Tetsuro Iwamura , Atsushi Kobayashi , Masahiko Motoyama , Hideki Teraoka , Atsushi Shimbo , Hideo Shimizu
发明人： Daijiro Kimbara , Hiroo Nakano , Tetsuro Iwamura , Atsushi Kobayashi , Masahiko Motoyama , Hideki Teraoka , Atsushi Shimbo , Hideo Shimizu
IPC分类号： G11C29/00
CPC分类号： G06F21/77 , G06F11/1016 , G06F2221/2121 , G06K19/07363 , G11C7/1006 , G11C2029/0411
摘要： A semiconductor storage device includes an arithmetic operation unit configured to perform an arithmetic operation of generating a different error detecting code depending on the information of a memory address, using the data and the information of the memory address in a memory cell into which the data is written, and a storage unit configured to store the data and the error detecting code in the memory cell.
摘要翻译：一种半导体存储装置，包括算术运算单元，其被配置为使用数据和存储器单元中的存储器地址的信息，根据存储器地址的信息执行生成不同的检错码的算术运算，以及存储单元，被配置为将数据和错误检测码存储在存储单元中。

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