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1. 发明申请

US20180005964A1 INTEGRATED CIRCUIT PROTECTION METHOD, AND CORRESPONDING INTEGRATED CIRCUIT 审中-公开
公开(公告)号：US20180005964A1
公开(公告)日：2018-01-04
申请号：US15446472
申请日：2017-03-01
申请人： STMicroelectronics (Rousset) SAS
发明人： Thomas Ordas , Alexandre Sarafianos , Fabrice Marinet , Stephane Chesnais
IPC分类号： H01L23/00 , H01L23/528 , H01L23/62 , H01L27/02
CPC分类号： H01L23/576 , G06F21/75 , G06F21/87 , G06K19/07327 , G06K19/07363 , H01L23/5227 , H01L23/528 , H01L23/62 , H01L27/0255
摘要： An integrated circuit includes a number of components disposed at a surface of a semiconductor body and an interconnect region connecting the components into a functional circuit. A metallic shield is also produced in the interconnect region. A configurable stage is configurable to operate in a receiving antenna configuration or in a detection configuration during which the integrated circuit is configured to detect a presence of an external electromagnetic radiation representative of an attack by injection of faults

2. 发明申请

US20170230169A1 SECURE DATA STORAGE 审中-公开
公开(公告)号：US20170230169A1
公开(公告)日：2017-08-10
申请号：US15424842
申请日：2017-02-04
申请人： NXP B.V.
发明人： Sebastien Riou
IPC分类号： H04L9/00 , G06F21/72 , G06F7/58 , H04L9/06
CPC分类号： H04L9/004 , G06F7/584 , G06F7/588 , G06F21/72 , G06K19/073 , G06K19/07309 , G06K19/07318 , G06K19/07363 , G09C1/00 , G11C7/24 , G11C13/0059 , H04L9/003 , H04L9/0643 , H04L9/0894
摘要： The disclosure relates to secure data storage and retrieval, in particular to methods and circuits for securely storing data to reduce the possibility of leakage via side channel attacks. Embodiments disclosed include a method of storing a value comprising a series of words, the method comprising: i) combining in a series of XOR operations a word of a first portion of the value, a word of a second portion of the value and an output word of a first random number generator to provide a first combined word; ii) storing the first combined word in a shift register; and iii) repeating steps i) and ii) for each successive word of the first and second portions of the value.

3. 发明授权

US09288038B2 Access-controlled data storage medium 有权
标题翻译：访问控制的数据存储介质
公开(公告)号：US09288038B2
公开(公告)日：2016-03-15
申请号：US13901262
申请日：2013-05-23
申请人： Giesecke & Devrient GmbH
发明人： Harald Vater , Hermann Drexler , Eric Johnson
IPC分类号： H04L9/00 , G06F21/77 , G06F21/55 , G06K19/073 , G07F7/08 , G07F7/10 , G06Q20/34
CPC分类号： H04L9/003 , G06F21/755 , G06F21/77 , G06K19/07363 , G06Q20/341 , G07F7/082 , G07F7/1008 , H04L2209/08
摘要： The invention relates to a data carrier having a semiconductor chip. In order to prevent an attacker from determining secret data of the chip from intercepted signal patterns of the chip, security-relevant operations are performed only with commands or command strings of the operating program whose use does not permit the processed data to be inferred from the signal patterns.
摘要翻译：本发明涉及具有半导体芯片的数据载体。为了防止攻击者从芯片的截取的信号模式中确定芯片的秘密数据，仅通过操作程序的命令或命令字符串执行与安全相关的操作，该操作程序的使用不允许从处理的数据推断处理的数据信号模式。

4. 发明授权

US09170297B2 Secure low pin count scan 有权
标题翻译：安全低引脚数扫描
公开(公告)号：US09170297B2
公开(公告)日：2015-10-27
申请号：US13715854
申请日：2012-12-14
申请人： NXP B.V.
发明人： Paul-Henri Pugliesi-Conti
IPC分类号： G01R31/3177 , G01R31/3185 , G06K19/073 , H04L9/00 , G01R31/40
CPC分类号： G01R31/3177 , G01R31/318547 , G01R31/318588 , G06K19/07363 , H04L9/002 , H04L2209/16
摘要： A contactless smartcard type integrated circuit needing only two pins for performing a standard ATPG test is disclosed. A scan test may be performed using one pin for the clock and the other pin for the input and input of the scan test data. Additionally, security is enhanced by using an embedded signature generator to avoid observation of the data shifted out.
摘要翻译：公开了仅需要两个引脚进行标准ATPG测试的非接触式智能卡式集成电路。可以使用时钟的一个引脚进行扫描测试，另一个引脚用于输入和输入扫描测试数据。另外，通过使用嵌入式签名生成器来避免对移出的数据的观察来增强安全性。

5. 发明申请

US20150052368A1 DIFFERENTIAL POWER ANALYSIS - RESISTANT CRYPTOGRAPHIC PROCESSING 审中-公开
标题翻译：差分功率分析 - 抗振动加工
公开(公告)号：US20150052368A1
公开(公告)日：2015-02-19
申请号：US14530905
申请日：2014-11-03
申请人： CRYPTOGRAPHY RESEARCH, INC.
发明人： PAUL C. KOCHER , JOSHUA M. JAFFE , BENJAMIN C. JUN
IPC分类号： H04L9/00 , G06F1/06 , G06F1/32
CPC分类号： H04L9/0618 , G06F1/06 , G06F1/266 , G06F1/3225 , G06F7/00 , G06F21/75 , G06F21/755 , G06F21/77 , G06F2207/7223 , G06F2207/7266 , G06K19/073 , G06K19/07363 , G06Q20/341 , G06Q20/382 , G06Q20/409 , G07F7/08 , G07F7/082 , G07F7/1008 , G09C1/00 , H04L9/003 , H04L2209/04 , H04L2209/08 , H04L2209/56 , H04L2209/805
摘要： Information leaked from smart cards and other tamper resistant cryptographic devices can be statistically analyzed to determine keys or other secret data. A data collection and analysis system is configured with an analog-to-digital converter connected to measure the device's consumption of electrical power, or some other property of the target device, that varies during the device's processing. As the target device performs cryptographic operations, data from the A/D converter are recorded for each cryptographic operation. The stored data are then processed using statistical analysis, yielding the entire key, or partial information about the key that can be used to accelerate a brute force search or other attack.
摘要翻译：从智能卡和其他防篡改加密设备泄露的信息可以进行统计分析，以确定密钥或其他秘密数据。数据采集和分析系统配置有连接的模拟 - 数字转换器，用于测量设备在设备处理期间变化的设备的电力消耗或目标设备的某些其他属性。当目标设备执行加密操作时，对于每个密码操作记录来自A / D转换器的数据。然后使用统计分析处理存储的数据，产生整个密钥，或者可以用于加速强力搜索或其他攻击的密钥的部分信息。

6. 发明授权

US08666070B2 Method and apparatus for minimizing differential power attacks on processors 有权
公开(公告)号：US08666070B2
公开(公告)日：2014-03-04
申请号：US11483553
申请日：2006-07-11
申请人： Farhad Pezeshki , Robert J. Lambert
发明人： Farhad Pezeshki , Robert J. Lambert
IPC分类号： H04L9/00
CPC分类号： H04L9/3247 , G06F7/725 , G06F9/30058 , G06F12/1408 , G06F21/52 , G06F21/75 , G06F21/755 , G06F2207/7223 , G06F2207/7242 , G06K19/073 , G06K19/07363 , H04L9/003 , H04L2209/04 , Y02D10/13
摘要： A method of masking a cryptographic operation using a secret value, comprising the steps of dividing the secret value into a plurality of parts; combining with each part a random value to derive a new part such that the new parts when combined are equivalent to the original secret value; and utilizing each of the individual parts in the operation.

7. 发明申请

US20130101112A1 METHOD AND APPARATUS FOR MINIMIZING DIFFERENTIAL POWER ATTACKS ON PROCESSORS 有权
标题翻译：用于最小化处理器上的不同功率攻击的方法和装置
公开(公告)号：US20130101112A1
公开(公告)日：2013-04-25
申请号：US13621021
申请日：2012-09-15
申请人： Farhad Pezeshki , Robert J. Lambert
发明人： Farhad Pezeshki , Robert J. Lambert
IPC分类号： H04L9/32
CPC分类号： H04L9/3247 , G06F7/725 , G06F9/30058 , G06F12/1408 , G06F21/52 , G06F21/75 , G06F21/755 , G06F2207/7223 , G06F2207/7242 , G06K19/073 , G06K19/07363 , H04L9/003 , H04L2209/04 , Y02D10/13
摘要： A method of masking a cryptographic operation using a secret value, comprising the steps of dividing the secret value into a plurality of parts; combining with each part a random value to derive a new part such that the new parts when combined are equivalent to the original secret value; and utilizing each of the individual parts in the operation.
摘要翻译：一种使用秘密值掩蔽密码操作的方法，包括以下步骤：将秘密值分割成多个部分; 与每个部分组合一个随机值以导出新的部分，使得当组合的新部分等同于原始秘密值时; 并且在操作中使用每个单独的部件。

8. 发明授权

US08296576B2 Method for scrambling the current consumption of an integrated circuit 有权
标题翻译：用于扰乱集成电路的电流消耗的方法
公开(公告)号：US08296576B2
公开(公告)日：2012-10-23
申请号：US10388324
申请日：2003-03-12
申请人： Sylvie Wuidart
发明人： Sylvie Wuidart
IPC分类号： G06F11/30 , G06F12/14 , G06F1/26 , G06F11/00 , G08B13/00 , G08B21/00 , G08B29/00
CPC分类号： H04K3/41 , G06F21/755 , G06K19/07363 , H01L23/585 , H01L24/06 , H01L2924/12035 , H01L2924/13091 , H01L2924/14 , H04K3/60 , H04K3/825 , H04K2203/20 , H01L2924/00
摘要： A method for scrambling current consumption of an integrated circuit, at least during execution of a confidential operation by the integrated circuit that includes reading confidential data stored therein and/or the calculation of an encryption code is provided. The charge pump is activated to generate current consumption fluctuations on the electrical power supply line of the integrated circuit, at an intensity great enough to mask the current consumption variations associated with the execution of the confidential operation.
摘要翻译：提供一种用于加扰集成电路的电流消耗的方法，至少在由包括读取存储在其中的机密数据和/或加密代码的计算的集成电路执行机密操作期间。电荷泵被激活以在集成电路的电源线上产生电流消耗波动，强度足以掩盖与执行机密操作相关联的当前消耗变化。

9. 发明申请

US20090147862A1 Semiconductor Device and IC Card Having The Same 审中-公开
标题翻译：具有相同的半导体器件和IC卡
公开(公告)号：US20090147862A1
公开(公告)日：2009-06-11
申请号：US11909921
申请日：2006-03-23
申请人： Shigeo Ohyama
发明人： Shigeo Ohyama
IPC分类号： H04B3/00
CPC分类号： H04L9/003 , G06K19/07363 , H04L2209/12
摘要： An IC card (1) includes: a plurality of circuit blocks (11 to 14); and an internal bus (21) which allows the circuit blocks to be connected to one another. Out of the circuit blocks, a CPU block (11) on an output side includes an encoding circuit (41) for outputting data to be transferred to a signal line (21a) of the data bus (22) after encoding the data in accordance with a predetermined encoding method so that variation of the data is evener, and a coprocessor block (12) on an input side includes a decoding circuit (42) for decoding the encoded data transferred via the signal line (21a). As a result, it is possible to realize (i) a semiconductor device which includes the plural circuit blocks and the internal signal line which allows the circuit blocks to be connected to one another but can decrease a possibility that data transferred among the circuit blocks may be estimated by power consumption analysis and (ii) an IC card having the semiconductor device.
摘要翻译： IC卡（1）包括：多个电路块（11至14）; 以及允许电路块彼此连接的内部总线（21）。在电路块中，输出侧的CPU块（11）包括编码电路（41），用于根据数据总线（22）的数据编码，输出要传送到数据总线（22）的信号线（21a）的数据一种预定的编码方法，使得数据的变化更加清晰，并且输入侧的协处理器块（12）包括用于对通过信号线（21a）传送的编码数据进行解码的解码电路（42）。结果，可以实现（i）包括多个电路块的半导体器件和允许电路块彼此连接的内部信号线，但是可以减少在电路块之间传送的数据的可能性通过功耗分析估计，以及（ii）具有半导体器件的IC卡。

10. 发明申请

US20090024887A1 SEMICONDUCTOR STORAGE DEVICE, DATA WRITE METHOD AND DATA READ METHOD 审中-公开
标题翻译：半导体存储器件，数据写入方法和数据读取方法
公开(公告)号：US20090024887A1
公开(公告)日：2009-01-22
申请号：US12032877
申请日：2008-02-18
申请人： Daijiro Kimbara , Hiroo Nakano , Tetsuro Iwamura , Atsushi Kobayashi , Masahiko Motoyama , Hideki Teraoka , Atsushi Shimbo , Hideo Shimizu
发明人： Daijiro Kimbara , Hiroo Nakano , Tetsuro Iwamura , Atsushi Kobayashi , Masahiko Motoyama , Hideki Teraoka , Atsushi Shimbo , Hideo Shimizu
IPC分类号： G11C29/00
CPC分类号： G06F21/77 , G06F11/1016 , G06F2221/2121 , G06K19/07363 , G11C7/1006 , G11C2029/0411
摘要： A semiconductor storage device includes an arithmetic operation unit configured to perform an arithmetic operation of generating a different error detecting code depending on the information of a memory address, using the data and the information of the memory address in a memory cell into which the data is written, and a storage unit configured to store the data and the error detecting code in the memory cell.
摘要翻译：一种半导体存储装置，包括算术运算单元，其被配置为使用数据和存储器单元中的存储器地址的信息，根据存储器地址的信息执行生成不同的检错码的算术运算，以及存储单元，被配置为将数据和错误检测码存储在存储单元中。

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