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    • 4. 发明授权
    • Camera and image output apparatus capable of trimmed photographing
    • 相机和图像输出设备能够修剪拍摄
    • US4929971A
    • 1990-05-29
    • US360245
    • 1989-06-01
    • Yoshio ImuraTsugio Takahashi
    • Yoshio ImuraTsugio Takahashi
    • G03B17/24G03B27/46
    • G03B17/24G03B27/462G03B2206/004G03B2217/243G03B2217/244G03B2217/246
    • A camera and an image output apparatus is capable of trimmed photographing. The camera is provided with detection means for detecting parallax information for specifying the difference between the photographing field and the viewing finder field based on the positional relationship between the photographing lens and the viewing finder, focal length of the photographing lens and object distance; and recording means for recording the parallax information detected by the detection means.The image output apparatus is provided with detection means for detecting the parallax information attached to the image information obtained in the above-mentioned camera; and means for printing or reproducing, on a cathode ray tube, the photographed image with trimming, corresponding to the finder viewing frame, according to the parallax information detected by the detection means.
    • 相机和图像输出装置能够进行裁剪。 摄像机设置有检测装置,用于根据摄影镜头和取景器之间的位置关系,拍摄镜头的焦距和物体距离,检测用于指定拍摄场和取景器场之间的差异的视差信息; 以及用于记录由检测装置检测的视差信息的记录装置。 图像输出装置设置有用于检测附加到在上述相机中获得的图像信息的视差信息的检测装置; 以及用于根据由检测装置检测到的视差信息在阴极射线管上打印或再现相应于取景器观看框的拍摄图像的装置。
    • 5. 发明授权
    • Flash taking lens shutter camera
    • 闪光拍摄镜头快门摄像头
    • US5023648A
    • 1991-06-11
    • US331304
    • 1989-03-31
    • Hiroshi MeguroTsugio TakahashiHitoshi AokiToru Kosaka
    • Hiroshi MeguroTsugio TakahashiHitoshi AokiToru Kosaka
    • G03B7/17G02B7/28G03B9/08G03B9/60G03B9/70G03B13/36G03B15/05
    • G03B9/70G03B9/60
    • A lens shutter camera comprises a mode signal output device for outputting either a first flash mode signal or a second flash mode signal, a shutter driving device for effecting the opening movement of the lens shutter slowly and effecting the closing movement of the lens shutter quickly when the first flash mode signal is being outputted, and for effecting both of the opening and closing movements of the lens shutter slowly when the second flash mode signal is being outputted, and a flash start signal output device for outputting a flash start signal during the opening movement of the lens shutter when the first flash mode signal is being outputted, and for outputting the flash start signal during the closing movement of the lens shutter when the second flash mode signal is being outputted.
    • 镜头快门摄像机包括用于输出第一闪光模式信号或第二闪光模式信号的模式信号输出装置,用于缓慢地进行透镜快门的打开运动并快速实现透镜快门的关闭运动的快门驱动装置, 正在输出第一闪光模式信号,并且用于当输出第二闪光模式信号时缓慢地实现透镜快门的打开和关闭运动;以及闪光启动信号输出装置,用于在打开期间输出闪光启动信号 当输出第一闪光模式信号时透镜快门的移动,并且当输出第二闪光模式信号时在透镜快门的关闭运动期间输出闪光开始信号。
    • 7. 再颁专利
    • Semiconductor memory
    • 半导体存储器
    • USRE38944E1
    • 2006-01-24
    • US09974962
    • 2001-10-12
    • Tsugio TakahashiGoro KitsukawaTakesada AkibaYasushi KawaseMasayuki Nakamura
    • Tsugio TakahashiGoro KitsukawaTakesada AkibaYasushi KawaseMasayuki Nakamura
    • G11C8/00
    • H01L27/10805G11C7/10G11C11/408G11C11/4096G11C11/4097H01L27/105
    • A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and columns selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
    • 具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。 每个子存储器垫包括:存储器阵列,其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器,包括对应于子字线的单元子字线驱动电路; 感测放大器,包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。 子存储垫以格子排列。 子存储垫上面是:主字线和列选择信号线与正交相交的层,主字线具有作为子字线的间距的整数倍的间距,列选择信号线具有 间距,是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。
    • 9. 发明授权
    • Semiconductor memory device using open data line arrangement
    • 半导体存储器件采用开放数据线布置
    • US06400596B2
    • 2002-06-04
    • US09725107
    • 2000-11-29
    • Riichiro TakemuraTomonori SekiguchiKatsutaka KimuraKazuhiko KajigayaTsugio Takahashi
    • Riichiro TakemuraTomonori SekiguchiKatsutaka KimuraKazuhiko KajigayaTsugio Takahashi
    • G11C1100
    • H01L27/10894G11C11/4097H01L27/10897
    • When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.
    • 当使用相移方法作为光刻技术时,将读出放大器交替放置在能够实现DRAM面积减小的一个交叉点存储器中,难以在读出放大器与每个读出放大器之间的边界区域中布置数据线 内存阵列 因此,提供了根据本发明的半导体器件。 在半导体器件中,在副存储器阵列内或插入其间的两条数据线被连接到相邻的读出放大器,作为用于当读出放大器交替地从子存储器阵列(SMA)到读出放大器(SA)的数据线绘制的系统 放置 即,分别连接到两个相邻读出放大器的数据线之间的数据线的数目被设置为偶数(0,2,4 ...)。 由于上述结构,可以避免在读出放大器块和子存储器阵列连接的部分中的断路和短路,并且便于连接布局。
    • 10. 发明授权
    • Semiconductor memory
    • 半导体存储器
    • US5966341A
    • 1999-10-12
    • US982398
    • 1997-12-02
    • Tsugio TakahashiGoro KitsukawaTakesada AkibaYasushi KawaseMasayuki Nakamura
    • Tsugio TakahashiGoro KitsukawaTakesada AkibaYasushi KawaseMasayuki Nakamura
    • G11C11/401G11C7/10G11C11/407G11C11/408G11C11/409G11C11/4096G11C11/4097H01L21/8242H01L27/105H01L27/108G11C13/00
    • H01L27/10805G11C11/408G11C11/4096G11C11/4097G11C7/10H01L27/105
    • A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
    • 具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。 每个子存储器垫包括:存储器阵列,其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器,包括对应于子字线的单元子字线驱动电路; 感测放大器,包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。 子存储垫以格子排列。 在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层,主字线具有作为子字线的间距的整数倍的间距,列选择信号线具有 间距,是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。