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1. 发明授权

US06807243B2 Delay clock generating apparatus and delay time measuring apparatus 失效
标题翻译：延迟时钟发生装置和延迟时间测量装置
公开(公告)号：US06807243B2
公开(公告)日：2004-10-19
申请号：US10421497
申请日：2003-04-23
申请人： Toshiyuki Okayasu , Shinya Sato
发明人： Toshiyuki Okayasu , Shinya Sato
IPC分类号： H04L2538
CPC分类号： H03L7/0995 , G01R31/31922
摘要： A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the downward shift of the shift clock 70 with the downward shift of the standard clock 34 to output a shift clock 72. The shift clock 72 is supplied to the pulse inserter 54. The phase controller 56 receives the standard clock 34 and generates a phase control signal 74 indicating cycles of the shift clock 72 to which the insert-pulses are inserted among a plurality of cycles of the shift clock 72. The pulse inserter 54 inserts the insert-pulses to the cycles of the shift clock indicated by the phase control signal 74. The phase-lock unit 58 generates a delay clock 82 by delaying the phase of the shift clock 70 oscillated by the ring oscillator 50 with respect to the phase of the standard clock, based on the standard clock and the shift clock 76 including the insert-pulses.
摘要翻译：标准时钟34输入到相位比较器52和相位控制器56.环形振荡器50振荡具有与标准时钟34相同周期的移位时钟70.相位比较器52将移位时钟70的向下移位与标准时钟34向下移动以输出移位时钟72.移位时钟72被提供给脉冲插入器54.相位控制器56接收标准时钟34并产生指示移位时钟72的周期的相位控制信号74 插入脉冲在移位时钟72的多个周期之间插入到其中。脉冲插入器54将插入脉冲插入由相位控制信号74指示的移位时钟的周期。相位锁定单元58产生通过基于标准时钟和包括插入脉冲的移位时钟76，延迟由环形振荡器50相对于标准时钟的相位振荡的移位时钟70的相位的延迟时钟82。

2. 发明授权

US06597753B1 Delay clock generating apparatus and delay time measuring apparatus 失效
标题翻译：延迟时钟发生装置和延迟时间测量装置
公开(公告)号：US06597753B1
公开(公告)日：2003-07-22
申请号：US09541910
申请日：2000-04-03
申请人： Toshiyuki Okayasu , Shinya Sato
发明人： Toshiyuki Okayasu , Shinya Sato
IPC分类号： H03D324
CPC分类号： H03L7/0995 , G01R31/31922
摘要： A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the downward shift of the shift clock 70 with the downward shift of the standard clock 34 to output a shift clock 72. The shift clock 72 is supplied to the pulse inserter 54. The phase controller 56 receives the standard clock 34 and generates a phase control signal 74 indicating cycles of the shift clock 72 to which the insert-pulses are inserted among a plurality of cycles of the shift clock 72. The pulse inserter 54 inserts the insert-pulses to the cycles of the shift clock indicated by the phase control signal 74. The phase-lock unit 58 generates a delay clock 82 by delaying the phase of the shift clock 70 oscillated by the ring oscillator 50 with respect to the phase of the standard clock, based on the standard clock and the shift clock 76 including the insert-pulses.
摘要翻译：标准时钟34输入到相位比较器52和相位控制器56.环形振荡器50振荡具有与标准时钟34相同周期的移位时钟70.相位比较器52将移位时钟70的向下移位与标准时钟34向下移动以输出移位时钟72.移位时钟72被提供给脉冲插入器54.相位控制器56接收标准时钟34并产生指示移位时钟72的周期的相位控制信号74 插入脉冲在移位时钟72的多个周期之间插入到其中。脉冲插入器54将插入脉冲插入由相位控制信号74指示的移位时钟的周期。相位锁定单元58产生通过基于标准时钟和包括插入脉冲的移位时钟76，延迟由环形振荡器50相对于标准时钟的相位振荡的移位时钟70的相位的延迟时钟82。

3. 发明授权

US06651179B1 Delay time judging apparatus 失效
标题翻译：延迟时间判断装置
公开(公告)号：US06651179B1
公开(公告)日：2003-11-18
申请号：US09568339
申请日：2000-05-10
申请人： Shinya Sato , Masatoshi Sato , Toshiyuki Okayasu
发明人： Shinya Sato , Masatoshi Sato , Toshiyuki Okayasu
IPC分类号： G06F104
CPC分类号： H03K5/135 , G01R31/3016 , H03K5/133 , H03K5/26 , H03L7/0814 , H04L7/0337
摘要： Apparatus of judging delay time, capable of judging whether or not delay time for delaying an input signal is equal to a desired delay, includes: a shift clock supply unit which supplies a shift clock whose phase is delayed by the desired delayed time against a phase of a reference clock; a phase comparing unit which compares a phase of the shift clock to a phase of a delay clock for which the reference clock is delayed by a delay circuit, and then outputs a comparison signal; and a judging unit which judges whether or not the delay time of the delay circuit is equal to the desired delay time. A method therefor includes: generating a shift clock which delays a phase of a reference clock by a predetermined amount based on a desired delay time; comparing a phase of the delay clock to that of the shift clock; judging whether or not the phase of the shift clock matches that of the delay clock; and repeating a step of generating the shift clock, a step of comparing the phase and a step of judging until the phase of the delay clock matches that of the shift clock.
摘要翻译：判断延迟时间的装置，能够判断延迟输入信号的延迟时间是否等于期望的延迟，包括：移位时钟提供单元，其向相位延迟所需延迟时间的移相时钟提供相位，的参考时钟; 相位比较单元，其将所述移位时钟的相位与所述参考时钟被延迟电路延迟的延迟时钟的相位进行比较，然后输出比较信号; 以及判断单元，判断延迟电路的延迟时间是否等于期望的延迟时间。其方法包括：产生基于期望的延迟时间将参考时钟的相位延迟预定量的移位时钟; 将延迟时钟的相位与移位时钟的相位进行比较; 判断移位时钟的相位是否与延迟时钟的相位相匹配; 以及重复产生移位时钟的步骤，比较所述相位和判断步骤直至所述延迟时钟的相位与所述移位时钟的相位相匹配的步骤。

4. 发明授权

US08892381B2 Test apparatus and manufacturing method 有权
标题翻译：试验装置及制造方法
公开(公告)号：US08892381B2
公开(公告)日：2014-11-18
申请号：US13044320
申请日：2011-03-09
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： G01R31/26 , G06F19/00 , G01R31/319 , G01R31/3185
CPC分类号： G01R31/318511 , G01R31/31926
摘要： A test apparatus that tests a plurality of devices under test formed on a wafer under test includes a test substrate that faces the wafer under test and is electrically connected to the devices under test, a programmable device that is provided on the test substrate and changes a logic relationship of output logic data with respect to input logic data, according to program data supplied thereto, a plurality of input/output circuits that are provided on the test substrate to correspond to the devices under test and that each supply the corresponding device under test with a test signal corresponding to the output logic data of the programmable device, and a judging section that judges pass/fail of each device under test, based on operation results of each device under test according to the test signal.
摘要翻译：测试在被测晶片上形成的多个待测器件的测试装置包括面向被测晶片并与被测器件电连接的测试基板，设置在测试基板上的可编程器件，输出逻辑数据相对于输入逻辑数据的逻辑关系，根据提供给其的程序数据，多个输入/输出电路，设置在测试基板上以对应于被测器件，并且每个输入/输出电路提供相应的被测器件具有与可编程装置的输出逻辑数据相对应的测试信号，以及判定部，根据测试信号，根据被测设备的运算结果，判定各被测设备的通过/失败。

5. 发明授权

US08537935B2 Clock data recovery circuit and method 失效
标题翻译：时钟数据恢复电路及方法
公开(公告)号：US08537935B2
公开(公告)日：2013-09-17
申请号：US12532132
申请日：2008-03-18
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： H03D3/18 , H03D3/24
CPC分类号： H04L7/033 , G01R31/31727 , G01R31/31937 , H03L7/0812 , H04L7/0037
摘要： A change-point detection circuit 16 extracts a clock signal from serial data, input data. A variable delay circuit provides a delay in accordance with a delay control signal to a reference signal having a predetermined frequency, so that the phase of the reference signal is shifted on the basis of an initial delay. An input latch circuit latches internal serial data by using an output signal of the variable delay circuit as a strobe signal. A phase comparator matches the frequencies of the clock signal and the strobe signal with each other, and generates phase difference data in accordance with a phase difference between the two signals. A loop filter integrates the phase difference data generated by the phase comparator and outputs it as the delay control signal. The phase shift amount acquisition unit acquires a phase shift amount based on the delay control signal, the phase shift amount being based on the initial delay provided to the reference signal by the variable delay circuit.
摘要翻译：变化点检测电路16从串行数据，输入数据中提取时钟信号。可变延迟电路根据具有预定频率的参考信号的延迟控制信号提供延迟，使得参考信号的相位基于初始延迟而偏移。输入锁存电路通过使用可变延迟电路的输出信号作为选通信号来锁存内部串行数据。相位比较器将时钟信号和选通信号的频率相互匹配，并根据两个信号之间的相位差产生相位差数据。环路滤波器对相位比较器产生的相位差数据进行积分，并将其作为延迟控制信号输出。相移量获取单元基于延迟控制信号获取相移量，相移量基于由可变延迟电路提供给参考信号的初始延迟。

6. 发明授权

US08466702B2 Test system and substrate unit for testing 有权
标题翻译：测试系统和基板单元进行测试
公开(公告)号：US08466702B2
公开(公告)日：2013-06-18
申请号：US12953352
申请日：2010-11-23
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： G01R31/20 , G01R31/02
CPC分类号： G01R31/2889
摘要： A test system that tests a plurality of chips under test formed on a wafer under test, the test system comprising a plurality of test substrates that are arranged in overlapping layers and that each have a plurality of test circuits, whose function is determined for each wafer, formed thereon; a plurality of connecting sections that electrically connect, to the chips under test, the test circuits formed on one of the test substrates; and a control apparatus that controls each of the test circuits. Each test substrate has test circuits, with a function predetermined for each substrate, formed thereon.
摘要翻译：一种在被测晶片上测试被测试的多个待测芯片的测试系统，所述测试系统包括多个测试基板，所述多个测试基板布置在重叠层中，并且每个具有多个测试电路，每个测试电路的功能是针对每个晶片，形成在其上多个连接部，其将与测试用芯片电连接的测试电路形成在一个测试基板上; 以及控制每个测试电路的控制装置。每个测试基板具有在其上形成的具有对于每个基板预定的功能的测试电路。

7. 发明授权

US08378700B2 Wafer unit for testing semiconductor chips and test system 有权
标题翻译：晶圆单元用于测试半导体芯片和测试系统
公开(公告)号：US08378700B2
公开(公告)日：2013-02-19
申请号：US12953362
申请日：2010-11-23
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： G01R31/20
CPC分类号： G01R31/2884 , G01R31/2831
摘要： Provided is a test wafer unit for testing a plurality of semiconductor chips formed on a semiconductor wafer, the test wafer unit including: a test wafer having a shape corresponding to a shape of the semiconductor wafer; and a plurality of test circuits formed on the test wafer, each test circuit provided to correspond to two or more of the plurality of semiconductor chips and testing the two or more semiconductor chips. The test wafer unit may include a plurality of connection terminals formed on the test wafer in one to one relation with test terminals of the plurality of semiconductor chips, where each of the plurality of connection terminals is connected to a corresponding one of the test terminals.
摘要翻译：提供了一种用于测试形成在半导体晶片上的多个半导体芯片的测试晶片单元，该测试晶片单元包括：具有对应于半导体晶片形状的形状的测试晶片; 以及形成在所述测试晶片上的多个测试电路，每个测试电路被提供以对应于所述多个半导体芯片中的两个或更多个并且测试所述两个或更多个半导体芯片。测试晶片单元可以包括与多个半导体芯片的测试端子成一一关系的在测试晶片上形成的多个连接端子，其中多个连接端子中的每一个连接到相应的一个测试端子。

8. 发明授权

US08375340B2 Apparatus for manufacturing substrate for testing, method for manufacturing substrate for testing and recording medium 有权
标题翻译：用于制造用于测试的基板的装置，用于测试和记录介质的基板的制造方法
公开(公告)号：US08375340B2
公开(公告)日：2013-02-12
申请号：US12952112
申请日：2010-11-22
申请人： Daisuke Watanabe , Masakatsu Suda , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Masakatsu Suda , Toshiyuki Okayasu
IPC分类号： G06F17/50
CPC分类号： G01R31/318511 , G01R31/31718
摘要： A test substrate manufacturing apparatus comprising a test circuit database that stores circuit data of a plurality of types of test circuits in association with a plurality of types of testing content; a definition information storing section that stores definition information defining arrangements of device pads of devices under test and testing content to be performed for each of the device pads; and a lithography data generating section that generates lithography data for the test substrate by (i) selecting, from the test circuit database, circuit data of each test circuit to be connected to a device pad based on the testing content defined by the definition information stored in the definition information storing section and (ii) determining positions on the test substrate where the test circuits corresponding to the selected circuit data are formed using lithography, based on the arrangements of the device pads as defined by the definition information.
摘要翻译：一种测试基板制造装置，包括：与多种测试内容相关联地存储多种类型的测试电路的电路数据的测试电路数据库; 定义信息存储部分，其存储定义要定义的装置的装置的定义信息，并且对每个装置焊盘执行测试内容; 以及光刻数据生成部，其通过以下步骤生成用于所述测试基板的光刻数据：（i）基于由所存储的所述定义信息定义的测试内容，从所述测试电路数据库中选择要连接到设备焊盘的每个测试电路的电路数据在定义信息存储部分中，以及（ii）基于由定义信息定义的装置焊盘的布置，确定测试基板上的位置，其中使用光刻形成与所选择的电路数据相对应的测试电路。

9. 发明申请

US20120319794A1 TEST APPARATUS FOR DIGITAL MODULATED SIGNAL 审中-公开
标题翻译：数字调制信号测试装置
公开(公告)号：US20120319794A1
公开(公告)日：2012-12-20
申请号：US13588823
申请日：2012-08-17
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： H03K7/00 , H03K9/00
CPC分类号： H04L27/34 , G01R31/31924 , H04L25/4917 , H04L27/362 , H04L27/38
摘要： A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers.
摘要翻译：测试装置包括以多个通道为增量提供的数字调制器。基带信号发生器使用可以调整定时信号的定时信号来执行数据输入的重新定时作为同相（正交）分量的调制信号，从而生成基带信号。驱动器产生具有与从基带信号发生器输出的基带信号对应的电平的多值数字信号。乘法器用多值数字信号对载波信号进行幅度调制。加法器对乘法器的输出信号求和。

10. 发明授权

US08270225B2 Data receiving circuit 失效
标题翻译：数据接收电路
公开(公告)号：US08270225B2
公开(公告)日：2012-09-18
申请号：US12532134
申请日：2008-03-18
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： G11C7/10
CPC分类号： G01R31/3191 , G01R31/31937
摘要： A variable delay circuit provides an adjustable delay to a strobe signal. An input latch circuit latches each bit data included in internal serial data by a strobe signal delayed by the variable delay circuit. A delay set unit adjusts a delay amount provided to the strobe signal by the variable delay circuit. While a calibration operation is being executed in which a known calibration pattern is inputted as serial data, the delay set unit statistically acquires output latch data of the input latch circuit, and adjusts the delay amount such that probabilities of occurrence of 1 and 0 becomes a predetermined ratio.
摘要翻译：可变延迟电路为选通信号提供可调延迟。输入锁存电路通过可变延迟电路延迟的选通信号来锁存内部串行数据中包含的每个位数据。延迟设定单元通过可变延迟电路来调整提供给选通信号的延迟量。当正在执行其中输入已知校准图案作为串行数据的校准操作时，延迟设置单元统计地获取输入锁存电路的输出锁存数据，并调整延迟量，使得出现1和0的概率变为预定比例。

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