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    • 3. 发明授权
    • CRC generator polynomial select method, CRC coding method and CRC coding circuit
    • CRC生成多项式选择方法,CRC编码方法和CRC编码电路
    • US08341510B2
    • 2012-12-25
    • US11821561
    • 2007-06-22
    • Masashi ShinagawaKeitarou KondouMakoto Noda
    • Masashi ShinagawaKeitarou KondouMakoto Noda
    • H03M13/09
    • H03M13/09H03M13/6508
    • Disclosed herein is a CRC generator polynomial select method for selecting a generator polynomial to be used in CRC coding and code checking, the method may include a first process of finding largest minimum Hamming distances Max.dmin of codes generated from given polynomials; a second process of finding code lengths n for codes having the largest minimum Hamming distances Max.dmin and determining a range nmin (r, Max.dmin)≦n≦nmax (r, Max.dmin); a third process of searching all polynomials for specific polynomials generating codes having dmin=Max.dmin in the determined range; and a fourth process of selecting final generator polynomials having a smallest non-zero coefficient count and a lowest code undetected-error probability from the specific polynomials.
    • 本发明公开了一种CRC生成多项式选择方法,用于选择要用于CRC编码和代码检查的生成多项式,该方法可以包括找到从给定多项式生成的代码的最大最小汉明距离Max.dmin的第一处理; 确定最小最小汉明距离Max.dmin的码的码长n的第二过程,并确定范围nmin(r,Max.dmin)≦̸ n≦̸ nmax(r,Max.dmin); 在确定的范围内搜索具有dmin = Max.dmin的代码的特定多项式的所有多项式的第三处理; 以及从特定多项式中选择具有最小非零系数计数和最低代码未检测错误概率的最终生成多项式的第四处理。
    • 5. 发明申请
    • Decoding apparatus and decoding method
    • 解码装置和解码方法
    • US20080056401A1
    • 2008-03-06
    • US11880465
    • 2007-07-20
    • Hiroyuki YamagishiKeitarou Kondou
    • Hiroyuki YamagishiKeitarou Kondou
    • H04L23/02
    • H04L25/497H04L25/03197
    • Disclosed herein is a decoding apparatus for decoding channel input bits from a partial-response channel output in accordance with a trellis obtained by combining a coding constraint and state transitions of a partial response for a case in which the length of a memory required for describing the coding constraint is greater than the length of a channel memory of the partial response. The apparatus may include a first calculation unit configured to carry out a first calculation on first branch information, which may be defined as information on first branches included in three or more branches merging in a state determined in advance, and first path information defined as information on first paths for the first branches; and a second calculation unit configured to carry out a second calculation on a first calculation value obtained as a result of the first calculation.
    • 本文公开了一种解码装置,用于根据通过组合编码约束和部分响应的状态转换而获得的网格来解码来自部分响应信道输出的信道输入比特,其中描述所需的存储器的长度 编码约束大于部分响应的通道存储器的长度。 该装置可以包括:第一计算单元,被配置为对第一分支信息执行第一计算,第一分支信息可以被定义为包括在预先确定的状态中合并的三个或更多个分支中的第一分支的信息和被定义为信息的第一路径信息 在第一个分支的第一条路上; 以及第二计算单元,被配置为对作为第一计算的结果获得的第一计算值执行第二计算。
    • 7. 发明授权
    • Decoding apparatus and decoding method
    • 解码装置和解码方法
    • US07860181B2
    • 2010-12-28
    • US11880465
    • 2007-07-20
    • Hiroyuki YamagishiKeitarou Kondou
    • Hiroyuki YamagishiKeitarou Kondou
    • H04L23/02
    • H04L25/497H04L25/03197
    • Disclosed herein is a decoding apparatus for decoding channel input bits from a partial-response channel output in accordance with a trellis obtained by combining a coding constraint and state transitions of a partial response for a case in which the length of a memory required for describing the coding constraint is greater than the length of a channel memory of the partial response. The apparatus may include a first calculation unit configured to carry out a first calculation on first branch information, which may be defined as information on first branches included in three or more branches merging in a state determined in advance, and first path information defined as information on first paths for the first branches; and a second calculation unit configured to carry out a second calculation on a first calculation value obtained as a result of the first calculation.
    • 本文公开了一种解码装置,用于根据通过组合编码约束和部分响应的状态转换而获得的网格来解码来自部分响应信道输出的信道输入比特,其中描述所需的存储器的长度 编码约束大于部分响应的通道存储器的长度。 该装置可以包括:第一计算单元,被配置为对第一分支信息执行第一计算,第一分支信息可以被定义为包括在预先确定的状态中合并的三个或更多个分支中的第一分支的信息和被定义为信息的第一路径信息 在第一个分支的第一条路上; 以及第二计算单元,被配置为对作为第一计算的结果获得的第一计算值执行第二计算。