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    • 6. 发明授权
    • Switching power supply device
    • 开关电源装置
    • US08339809B2
    • 2012-12-25
    • US12721963
    • 2010-03-11
    • Yasuhiro Nakata
    • Yasuhiro Nakata
    • H02M3/335
    • H02M3/3385H02M1/36
    • A switching power supply device includes a transformer, a switching unit which is connected with a primary winding of the transformer and configured to switch a current flowing to the primary winding, a start unit configured to start the switching unit, a voltage drop unit configured to lower output voltage from a secondary winding of the transform, and a current control unit configured to control an amount of a current flowing in the start unit when the switching unit is in an off state by lowering output voltage by the voltage drop unit.
    • 开关电源装置包括变压器,开关单元,其与变压器的初级绕组连接并且被配置为切换流过初级绕组的电流;起动单元,被配置为启动开关单元;电压降单元,被配置为 所述变流器的次级绕组的输出电压较低;以及电流控制单元,被配置为通过降低所述电压降单元的输出电压来控制在所述开关单元处于断开状态时流过所述启动单元的电流量。
    • 8. 发明申请
    • Chip inductor and method for manufacturing the same
    • 片式电感及其制造方法
    • US20070069844A1
    • 2007-03-29
    • US10556700
    • 2004-11-17
    • Hayami KudoMasahiko KawaguchiYasuhiro Nakata
    • Hayami KudoMasahiko KawaguchiYasuhiro Nakata
    • H01F27/02
    • H01F17/0013H01F41/041H01F2017/002
    • A chip inductor in which excellent Q characteristic is realized while advantages in its small size and low profile are ensured, as well as a method for manufacturing the same, is provided. A chip inductor 1 is constructed by alternately laminating plural conductor patterns 31, 32, 33, and 34 and plural insulating layers 35, 36, 37, and 38 on and above a ceramic substrate 2, and connecting these plural conductor patterns 31, 32, 33, and 34 to each other in series in the lamination direction thereof so as to constitute a coil 30. Specifically, the number of turns of the lowermost-layer conductor pattern 31 disposed immediately on the ceramic substrate 2 is specified to be larger than the numbers of turns of the other plural conductor patterns 32, 33, and 34, and the numbers of turns of the other plural conductor patterns 32, 33, and 34 are specified to be substantially equal to each other. Preferably, the number of turns of the conductor pattern 31 is specified to be about 1.5 times the numbers of turns of the other plural conductor patterns 32, 33, and 34.
    • 提供确保了其小尺寸和低外形优点的优异Q特性的片式电感器及其制造方法。 芯片电感器1是通过在陶瓷基板2上和之上交替层叠多个导体图案31,32,33,34以及多个绝缘层35,36,37,38并将这些多个导体图案31,32,32,38连接起来而构成的。 33和34彼此在层叠方向上串联以构成线圈30.具体地说,紧接在陶瓷基板2上设置的最下层导体图案31的匝数被规定为大于 其他多个导体图案32,33,34的匝数和其他多个导体图案32,33,34的匝数被规定为大致相等。 优选地,导体图案31的匝数被规定为其他多个导体图案32,33和34的匝数的约1.5倍。
    • 10. 发明授权
    • Multilayer noise filter including integral damping resistor
    • 多层噪声滤波器,包括积分阻尼电阻
    • US6160461A
    • 2000-12-12
    • US67441
    • 1998-04-28
    • Takahiro AzumaYasuhiro Nakata
    • Takahiro AzumaYasuhiro Nakata
    • H01F27/00H01F17/00H01G4/40H03H7/06H03H7/075
    • H03H7/06
    • A multilayer noise filter includes a damping resistor which is arranged to control the distortion of the waveform of an output signal and eliminate a space required for installation of the damping resistor on a substrate upon which the filter is mounted. The axial direction of coils incorporated in inductor assemblies is substantially perpendicular to external input and output electrodes. One end of one coil is electrically connected to the external input electrode and one end of another coil is electrically connected to the external output electrode. The other ends of the coils are electrically connected to a resistor at different locations, respectively. The resistor connecting the external input and output electrodes is disposed on the top surface of a multilayer unit such that the resistor is substantially parallel to the stacking direction of the multilayer unit and the axial direction of the coils. In a capacitor assembly, a pair of capacitor conductors are arranged to face each other.
    • 多层噪声滤波器包括阻尼电阻器,其被布置成控制输出信号的波形的失真,并消除在安装滤波器的基板上安装阻尼电阻所需的空间。 结合在电感器组件中的线圈的轴向方向基本上垂直于外部输入和输出电极。 一个线圈的一端电连接到外部输入电极,另一个线圈的一端电连接到外部输出电极。 线圈的另一端分别电连接到不同位置处的电阻器。 连接外部输入和输出电极的电阻器设置在多层单元的顶表面上,使得电阻器基本上平行于多层单元的层叠方向和线圈的轴向。 在电容器组件中,一对电容器导体被布置成彼此面对。