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    • 1. 发明授权
    • Surface acoustic wave device
    • 表面声波装置
    • US07944125B2
    • 2011-05-17
    • US12813550
    • 2010-06-11
    • Norihiko TakadaHayami Kudo
    • Norihiko TakadaHayami Kudo
    • H01L41/04H03H9/25
    • H03H9/1092H03H9/02897H03H9/1071Y10T156/1052
    • A surface acoustic wave device causing less wear of a dicing blade and causing less drop in a dicing speed is manufactured from a mother laminate with high yield and high precision. The surface acoustic wave device is manufactured by dicing a piezoelectric wafer. The surface acoustic wave device includes a piezoelectric substrate resulting from dicing the piezoelectric wafer, IDT electrodes and pad electrodes located on a top surface of the piezoelectric substrate. A support layer having an opening opened to the IDT electrodes is provided. An outline edge of the support layer is inside an outline edge of the top surface of the piezoelectric substrate. A cover made of an insulating material is disposed on the support layer to close the opening of the support layer. In plan view, the outline edge of the cover is aligned with the outline edge of the piezoelectric substrate.
    • 以高产率和高精度从母层压板制造引起切割刀片磨损较小并且切割速度降低较少的表面声波装置。 表面声波装置通过切割压电晶片来制造。 声表面波装置包括压电基片,其压电基片的顶表面上形成压电晶片,IDT电极和焊盘电极。 提供了具有向IDT电极开口的开口的支撑层。 支撑层的轮廓边缘在压电基板的顶表面的轮廓边缘的内侧。 由绝缘材料制成的盖子设置在支撑层上以封闭支撑层的开口。 在平面图中,盖的轮廓边缘与压电基板的轮廓边缘对齐。
    • 4. 发明申请
    • SURFACE ACOUSTIC WAVE DEVICE AND MANUFACTURING METHOD THEREOF
    • 表面声波装置及其制造方法
    • US20100253182A1
    • 2010-10-07
    • US12813550
    • 2010-06-11
    • Norihiko TAKADAHayami Kudo
    • Norihiko TAKADAHayami Kudo
    • H01L41/047H01L41/053B32B38/10H01L41/22
    • H03H9/1092H03H9/02897H03H9/1071Y10T156/1052
    • A surface acoustic wave device causing less wear of a dicing blade and causing less drop in a dicing speed is manufactured from a mother laminate with high yield and high precision. The surface acoustic wave device is manufactured by dicing a piezoelectric wafer. The surface acoustic wave device includes a piezoelectric substrate resulting from dicing the piezoelectric wafer, IDT electrodes and pad electrodes located on a top surface of the piezoelectric substrate. A support layer having an opening opened to the IDT electrodes is provided. An outline edge of the support layer is inside an outline edge of the top surface of the piezoelectric substrate. A cover made of an insulating material is disposed on the support layer to close the opening of the support layer. In plan view, the outline edge of the cover is aligned with the outline edge of the piezoelectric substrate.
    • 以高产率和高精度从母层压板制造引起切割刀片磨损较小并且切割速度降低较少的表面声波装置。 表面声波装置通过切割压电晶片来制造。 声表面波装置包括压电基片,其压电基片的顶表面上形成压电晶片,IDT电极和焊盘电极。 提供了具有向IDT电极开口的开口的支撑层。 支撑层的轮廓边缘在压电基板的顶表面的轮廓边缘的内侧。 由绝缘材料制成的盖子设置在支撑层上以封闭支撑层的开口。 在平面图中,盖的轮廓边缘与压电基板的轮廓边缘对齐。
    • 5. 发明申请
    • Chip inductor and method for manufacturing the same
    • 片式电感及其制造方法
    • US20070069844A1
    • 2007-03-29
    • US10556700
    • 2004-11-17
    • Hayami KudoMasahiko KawaguchiYasuhiro Nakata
    • Hayami KudoMasahiko KawaguchiYasuhiro Nakata
    • H01F27/02
    • H01F17/0013H01F41/041H01F2017/002
    • A chip inductor in which excellent Q characteristic is realized while advantages in its small size and low profile are ensured, as well as a method for manufacturing the same, is provided. A chip inductor 1 is constructed by alternately laminating plural conductor patterns 31, 32, 33, and 34 and plural insulating layers 35, 36, 37, and 38 on and above a ceramic substrate 2, and connecting these plural conductor patterns 31, 32, 33, and 34 to each other in series in the lamination direction thereof so as to constitute a coil 30. Specifically, the number of turns of the lowermost-layer conductor pattern 31 disposed immediately on the ceramic substrate 2 is specified to be larger than the numbers of turns of the other plural conductor patterns 32, 33, and 34, and the numbers of turns of the other plural conductor patterns 32, 33, and 34 are specified to be substantially equal to each other. Preferably, the number of turns of the conductor pattern 31 is specified to be about 1.5 times the numbers of turns of the other plural conductor patterns 32, 33, and 34.
    • 提供确保了其小尺寸和低外形优点的优异Q特性的片式电感器及其制造方法。 芯片电感器1是通过在陶瓷基板2上和之上交替层叠多个导体图案31,32,33,34以及多个绝缘层35,36,37,38并将这些多个导体图案31,32,32,38连接起来而构成的。 33和34彼此在层叠方向上串联以构成线圈30.具体地说,紧接在陶瓷基板2上设置的最下层导体图案31的匝数被规定为大于 其他多个导体图案32,33,34的匝数和其他多个导体图案32,33,34的匝数被规定为大致相等。 优选地,导体图案31的匝数被规定为其他多个导体图案32,33和34的匝数的约1.5倍。
    • 6. 发明授权
    • Piezoelectric device
    • 压电元件
    • US08067879B2
    • 2011-11-29
    • US12836595
    • 2010-07-15
    • Hayami KudoYuichi TakamineKatsuhiro Ikada
    • Hayami KudoYuichi TakamineKatsuhiro Ikada
    • H01L41/053H03H9/25
    • H03H9/1092H01L2224/05001H01L2224/05022H01L2224/05644H01L2224/05655H01L2224/13H03H9/059H01L2924/00014
    • A piezoelectric device includes a piezoelectric substrate, a conductive pattern which is provided on one main surface of the piezoelectric substrate and which includes an IDT electrode, a supporting layer which is arranged on the one main surface of the piezoelectric substrate so as to surround the periphery of an IDT-forming region in which the IDT electrode is provided and which has a thickness greater than that of the IDT electrode, and a cover layer which is arranged on the supporting layer and which covers the IDT-forming region. The supporting layer includes removed sections provided at a plurality of positions at least in a region close to the IDT-forming region, the removed sections being obtained by partially removing a portion of the supporting layer to be bonded to the one main surface of the piezoelectric substrate.
    • 一种压电装置,包括压电基板,设置在压电基板的一个主表面上并具有IDT电极的导电图案,支撑层布置在压电基板的一个主表面上以围绕周边 的IDT形成区域,其中设置有IDT电极并且其厚度大于IDT电极的厚度;以及覆盖层,其被布置在支撑层上并覆盖IDT形成区域。 支撑层包括设置在至少在靠近IDT形成区域的区域中的多个位置处的去除部分,所述去除部分通过部分地去除要结合到压电体的一个主表面的支撑层的一部分而获得 基质。