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1. 发明授权

US5701443A System for evaluating the results of logic simulation 失效
标题翻译：用于评估逻辑仿真结果的系统
公开(公告)号：US5701443A
公开(公告)日：1997-12-23
申请号：US640406
申请日：1996-04-29
申请人： Toshio Oguma , Yoshinobu Okazaki , Osamu Tada , Shigeki Yokotani
发明人： Toshio Oguma , Yoshinobu Okazaki , Osamu Tada , Shigeki Yokotani
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A logic simulation system for simulating a quality of logic description of a tested electric circuit includes a storage for storing execution results of logic simulation which was conducted for the electric circuit in the past and for which operations of the circuit have been confirmed, logic description to be tested for the electric circuit, and test data of the logic description to be tested. Logic simulation is conducted according to the test data and the logic description to be tested. Results of the logic simulation are compared with the past logic simulation results of operation by correcting time values according to a predetermined rule so as to simulate quality of the logic description, thereby outputting quality of the logic description in a visible form.
摘要翻译：用于模拟测试电路的逻辑描述的质量的逻辑模拟系统包括用于存储对过去的电路进行的逻辑模拟的执行结果的存储器，并且已经确认了电路的操作，逻辑描述对电路进行测试，并对要测试的逻辑描述进行测试数据。根据测试数据和要测试的逻辑描述进行逻辑仿真。通过根据预定规则校正时间值，将逻辑仿真结果与过去的逻辑仿真结果进行比较，以模拟逻辑描述的质量，从而以可见的形式输出逻辑描述的质量。

2. 发明授权

US5875116A Logic division apparatus 失效
标题翻译：逻辑分割装置
公开(公告)号：US5875116A
公开(公告)日：1999-02-23
申请号：US588236
申请日：1996-01-18
申请人： Toshio Oguma , Osamu Tada
发明人： Toshio Oguma , Osamu Tada
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： The electronic circuits of a large-scale ASIC or logic device are assigned to a plurality of programmable chips with logic block division that enables the finished circuits to operate at appropriate timings. A logic division processing unit divides the electronic circuits into a plurality of groups for automatic assignment to a plurality of programmable chips. A checking unit determines whether the designated logic blocks are accommodated in one programmable chip, and a division processing unit determines which logic blocks are to be assigned and the order of assignment priorities when the designated logic blocks are not all accommodated in the same programmable chip.
摘要翻译：大规模ASIC或逻辑器件的电子电路被分配给具有逻辑块划分的多个可编程芯片，使得成品电路能够在适当的定时运行。逻辑分割处理单元将电子电路分为多个组，用于自动分配给多个可编程芯片。检查单元确定指定的逻辑块是否被容纳在一个可编程芯片中，并且分割处理单元确定哪个逻辑块将被分配，并且当指定的逻辑块不全部被容纳在相同的可编程芯片中时，分配优先级的顺序。

3. 发明授权

US5911061A Program data creating method and apparatus for use with programmable devices in a logic emulation system 失效
标题翻译：用于与逻辑仿真系统中的可编程器件一起使用的程序数据创建方法和装置
公开(公告)号：US5911061A
公开(公告)日：1999-06-08
申请号：US692626
申请日：1996-08-06
申请人： Tatsuya Tochio , Osamu Tada , Toshio Oguma , Kazunobu Morimoto , Mototsugu Fujii
发明人： Tatsuya Tochio , Osamu Tada , Toshio Oguma , Kazunobu Morimoto , Mototsugu Fujii
IPC分类号： G05B19/05 , G06F17/50 , G06F17/00
CPC分类号： G06F17/5027 , G06F17/5054
摘要： A program data creating method and apparatus for use with programmable devices in a logic emulation system provides high-speed logic emulation of an LSI for logic and function verification. The logic data defining the logic circuits of the LSI is divided into a plurality of unit blocks in a layout analogous to the floor plan represented by floor plan information for the LSI. The unit blocks are allocated to the programmable devices automatically. The names of the signals defined within the design data regarding the LSI are made to correspond with the names of the signals in effect when the design data is deployed within the programmable devices, after optimization of the logic. This allows the program data for the programmable devices to be created and corrected using the signal names as set forth in the design data.
摘要翻译：用于逻辑仿真系统中的可编程器件的程序数据创建方法和装置提供用于逻辑和功能验证的LSI的高速逻辑仿真。定义LSI的逻辑电路的逻辑数据以类似于用于LSI的平面图信息表示的平面图的布局被划分为多个单元块。单位块自动分配给可编程设备。在设计数据中定义的关于LSI的信号的名称在逻辑优化之后被设计成与设计数据部署在可编程设备内部时有效的信号的名称相对应。这允许使用设计数据中所阐述的信号名称来创建和校正可编程器件的程序数据。

4. 发明授权

US5561281A Automatic transaction apparatus for cash transaction 失效
标题翻译：自动交易设备进行现金交易
公开(公告)号：US5561281A
公开(公告)日：1996-10-01
申请号：US334327
申请日：1994-11-02
申请人： Masaru Eda , Toshio Oguma
发明人： Masaru Eda , Toshio Oguma
IPC分类号： G07D9/00 , G06Q20/18 , G06Q40/00 , G06Q40/02 , G07D11/00 , G07F9/02 , G07F19/00 , G06F17/60
CPC分类号： G07F19/20 , G07D11/0006 , G07D11/0048 , G07D11/0057 , G07F19/202 , G07F9/02
摘要： Each of multiple cash cassettes is provided with a light-emission type push-button switch capable of indicating the operation state of the cash cassette and the need to exchange the cash cassette. By depressing the push-button switch, the associated cash cassette is separated from the cash transaction operation under the control of a CPU. When a customer is in front of a transaction apparatus or while a cash transaction is being carried out, a lamp of the push-button switch associated with the cash cassette, from which banknotes may be taken out in a subsequent dispensing operation, is flickered at a cycle of 1 second. When banknotes are replenished in the cash cassette, the banknotes can be replenished without suspending the operation of the apparatus, and the operation efficiency and operability of the apparatus can be enhanced.
摘要翻译：多个现金盒中的每一个都设置有能够指示现金盒的操作状态的发光型按钮开关和需要更换现金卡。通过按下按钮开关，相关联的现金盒在CPU的控制下与现金交易操作分离。当客户在交易装置的前面或正在执行现金交易时，与随后的分配操作中可从中取出纸币的现金盒相关联的按钮开关的灯闪烁在 1秒的周期。当在现金盒中补充纸币时，可以补充纸币而不中断装置的操作，并且可以提高装置的操作效率和可操作性。

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