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1. 发明授权

US5701443A System for evaluating the results of logic simulation 失效
标题翻译：用于评估逻辑仿真结果的系统
公开(公告)号：US5701443A
公开(公告)日：1997-12-23
申请号：US640406
申请日：1996-04-29
申请人： Toshio Oguma , Yoshinobu Okazaki , Osamu Tada , Shigeki Yokotani
发明人： Toshio Oguma , Yoshinobu Okazaki , Osamu Tada , Shigeki Yokotani
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A logic simulation system for simulating a quality of logic description of a tested electric circuit includes a storage for storing execution results of logic simulation which was conducted for the electric circuit in the past and for which operations of the circuit have been confirmed, logic description to be tested for the electric circuit, and test data of the logic description to be tested. Logic simulation is conducted according to the test data and the logic description to be tested. Results of the logic simulation are compared with the past logic simulation results of operation by correcting time values according to a predetermined rule so as to simulate quality of the logic description, thereby outputting quality of the logic description in a visible form.
摘要翻译：用于模拟测试电路的逻辑描述的质量的逻辑模拟系统包括用于存储对过去的电路进行的逻辑模拟的执行结果的存储器，并且已经确认了电路的操作，逻辑描述对电路进行测试，并对要测试的逻辑描述进行测试数据。根据测试数据和要测试的逻辑描述进行逻辑仿真。通过根据预定规则校正时间值，将逻辑仿真结果与过去的逻辑仿真结果进行比较，以模拟逻辑描述的质量，从而以可见的形式输出逻辑描述的质量。

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