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    • 5. 发明申请
    • Semiconductor nonvolatile storage circuit
    • 半导体非易失性存储电路
    • US20070274127A1
    • 2007-11-29
    • US10594220
    • 2005-03-30
    • Kazuyuki Nakamura
    • Kazuyuki Nakamura
    • G11C11/40G11C11/34G11C7/00
    • G11C11/404
    • A semiconductor nonvolatile storage circuit capable of stably storing and holding information by preventing pseudo-writing in storing/holding FETs is realized. The semiconductor nonvolatile circuit includes a first FET MNM1 forming a source-drain path between a ground potential GND and a bit line BL; a second FET MNM2 forming a source-drain path between the ground potential GND and a differential pair line BL_; a third FET MNM3 to open/close the connection between a drain terminal of the first FET MNM1 and the bit line BL; and a fourth FET MNM4 to open/close the connection between a drain terminal of the second FET MNM2 and the differential pair line BL_.
    • 实现了通过防止在存储/保持FET中的伪写入来稳定地存储和保持信息的半导体非易失性存储电路。 半导体非易失性电路包括形成地电位GND和位线BL之间的源 - 漏路径的第一FET MNM 1; 在接地电位GND和差分对线BL_之间形成源极 - 漏极路径的第二FET MNM 2; 第三FET MNM 3,用于打开/关闭第一FET MNM 1的漏极端子与位线BL之间的连接; 以及第四FET MNM4,以打开/关闭第二FET MNM 2的漏极端子和差分对线BL_之间的连接。
    • 6. 发明授权
    • CMIS semiconductor nonvolatile storage circuit
    • CMIS半导体非易失性存储电路
    • US07248507B2
    • 2007-07-24
    • US11637481
    • 2006-12-12
    • Kazuyuki Nakamura
    • Kazuyuki Nakamura
    • G11C8/00
    • G11C14/00G11C16/0466
    • A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a predetermined potential, a second MIS transistor having a second gate coupled to the selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to the predetermined potential, and a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node, wherein the selection line is operative to supply a write potential that creates a lingering change in a threshold voltage of one of the first MIS transistor and the second MIS transistor.
    • 非易失性半导体存储器电路包括选择线,第一位线,第二位线,具有耦合到选择线的第一栅极的第一MIS晶体管,经由第一节点耦合到第一位线的第一漏极,以及 耦合到预定电位的第一源极,具有耦合到选择线的第二栅极的第二MIS晶体管,经由第二节点耦合到第二位线的第二漏极和耦合到预定电位的第二源极,以及锁存电路 耦合到所述第一节点和所述第二节点以响应于所述第一节点和所述第二节点之间的信号差存储数据,其中所述选择线可操作以提供写入电位,所述写入电位在所述第一节点和所述第二节点之一的阈值电压中产生延迟变化 第一MIS晶体管和第二MIS晶体管。