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1. 发明申请

US20140222653A1 METHOD AND PROGRAM FOR DETECTING CHANGE-POINT OF TIME-SERIES DATA, AND METHOD AND PROGRAM FOR PREDICTING PROBABILITY DENSITY DISTRIBUTION OF FUTURE TIME-SERIES DATA VALUES 审中-公开
标题翻译：用于检测时间序列数据变化的方法和程序，以及用于预测未来时间序列数据值的概率密度分布的方法和程序
公开(公告)号：US20140222653A1
公开(公告)日：2014-08-07
申请号：US14343738
申请日：2012-09-07
申请人： Misako Takayasu , Yoshihiro Yura , Kazuyuki Nakamura
发明人： Misako Takayasu , Yoshihiro Yura , Kazuyuki Nakamura
IPC分类号： G06Q40/04 , G06Q30/02
CPC分类号： G06Q40/04 , G06Q30/0283
摘要： The present invention applies a particle filter method to the PUCK model for calculating a true market price. First, a probability density function of a parameter is obtained by generating a group of particles having parameters representing the state of the PUCK model each having different values. Then, the degree of conformity of each of the particles is evaluated and the particles are resampled as follows in accordance with the degree of conformity. A random number is compared with a predetermined value, where particles are regenerated in accordance with probability density function such as a normal distribution for making a parameter value of the model at time (t) into a mean value when the random number is greater than the predetermined value, and where the particles are regenerated taking a uniform distribution as the probability density function when the random number is less than the predetermined value.
摘要翻译：本发明在PUCK模型中应用粒子滤波器方法来计算真正的市场价格。首先，通过生成具有表示每个具有不同值的PUCK模型的状态的参数的一组粒子来获得参数的概率密度函数。然后，评价每个颗粒的一致性程度，根据合格度将颗粒重新采样如下。将随机数与预定值进行比较，其中根据诸如正态分布的概率密度函数来再现粒子，使得当时间（t）将模型的参数值设置为当随机数大于预定值，并且当随机数小于预定值时，将颗粒再生成均匀分布作为概率密度函数。

2. 发明申请

US20100115352A1 METHOD FOR EVALUATING SRAM MEMORY CELL AND COMPUTER READABLE RECORDING MEDIUM WHICH RECORDS EVALUATION PROGRAM OF SRAM MEMORY CELL 有权
标题翻译：用于评估SRAM存储单元的方法和计算机可读记录介质，其记录SRAM存储器单元的评估程序
公开(公告)号：US20100115352A1
公开(公告)日：2010-05-06
申请号：US12594048
申请日：2008-03-10
申请人： Kazuyuki NAKAMURA
发明人： Kazuyuki NAKAMURA
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5002
摘要： A method for evaluating an SRAM memory cell in which the time required for designing the SRAM memory cell can be shortened by evaluating static noise margin in a shortened time. A recording medium which records an evaluation program is also provided. The coordinate conversion which rotates the coordinate axis by 45 degrees is applied to the input/output characteristic data of a first inverter of the SRAM memory cell, and the first proximity curve function is specified by fitting the input/output characteristic data of the first inverter to the proximity curve. The coordinate conversion which rotates the coordinate axis by 45 degrees is applied to the input/output characteristic data of a second inverter of the SRAM memory cell, and the second proximity curve function is specified by fitting the input/output characteristic data of the second inverter to the proximity curve. A third proximity curve function which is a function generated by mirror-inverting the second proximity curve function with respect to the Y axis is specified, and a static noise margin is specified based on an extremal value of a difference curve function which is the difference between the first proximity curve function and the third proximity curve function.
摘要翻译：一种用于评估SRAM存储单元的方法，其中可以通过在缩短的时间内评估静态噪声容限来缩短设计SRAM存储单元所需的时间。还提供了记录评估程序的记录介质。将坐标轴旋转45度的坐标转换施加到SRAM存储单元的第一反相器的输入/输出特性数据，并且通过拟合第一反相器的输入/输出特性数据来指定第一接近曲线函数到接近曲线。将坐标轴旋转45度的坐标转换施加到SRAM存储单元的第二反相器的输入/输出特性数据，并且通过拟合第二反相器的输入/输出特性数据来指定第二接近曲线函数到接近曲线。指定作为通过相对于Y轴反转第二接近曲线函数而产生的函数的第三接近曲线函数，并且基于差分曲线函数的极值来指定静态噪声容限，该差分曲线函数是第一接近曲线函数和第三接近曲线函数。

3. 发明申请

US20100020625A1 ELECTRONIC CIRCUIT DEVICE 有权
标题翻译：电子电路设备
公开(公告)号：US20100020625A1
公开(公告)日：2010-01-28
申请号：US12526576
申请日：2008-01-29
申请人： Hiroyuki Morimoto , Kazuyuki Nakamura
发明人： Hiroyuki Morimoto , Kazuyuki Nakamura
IPC分类号： G11C7/00 , G11C8/00 , G11C5/14
CPC分类号： G05F1/56
摘要： To provide an electronic circuit device that can change a characteristic after package sealing and that achieves a reduction in miscellaneous tasks during characteristic setting.The electronic circuit device includes: a burst detecting circuit 7 for detecting, from an input and output terminal 4, a prescribed write activation burst having a length that is larger than or equal to a prescribed time; a signal-pattern detecting circuit 9 for putting a serial interface 8 into an input-enable state in which setting data can be input, when the write activation burst is detected; and a volatile memory 10 and a nonvolatile memory 11 for storing, in the input-enable state, a setting-data signal input from the input and output terminal 4. An operation state of a functional circuit 6 is set in accordance with the setting data written in the volatile memory 10 or the nonvolatile memory 11.
摘要翻译：提供能够改变包装密封后的特性的电子电路装置，并且在特征设定期间实现杂项任务的减少。电子电路装置包括：突发检测电路7，用于从输入和输出端子4检测具有大于或等于规定时间的长度的规定的写入激活脉冲串; 当检测到写入激活脉冲串时，将串行接口8置于能够输入设定数据的输入使能状态的信号图案检测电路9; 以及易失性存储器10和非易失性存储器11，用于在输入使能状态下存储从输入和输出端子4输入的设定数据信号。功能电路6的操作状态根据设定数据写入易失性存储器10或非易失性存储器11中。

4. 发明申请

US20090257879A1 RUNNER VANE FOR AXIAL-FLOW HYDRAULIC MACHINERY 有权
标题翻译：轴流式液压机械的运行范围
公开(公告)号：US20090257879A1
公开(公告)日：2009-10-15
申请号：US12421910
申请日：2009-04-10
申请人： Kazuyuki Nakamura , Norio Ohtake , Sakito Anpuku
发明人： Kazuyuki Nakamura , Norio Ohtake , Sakito Anpuku
IPC分类号： F03B3/12
CPC分类号： F03B13/105 , F03B3/126 , F03B11/04 , F05B2250/71 , F05B2250/711 , Y02E10/22 , Y02E10/223 , Y02E10/226 , Y10T29/49321
摘要： A camber line in a radial section of a runner vane has a curved part extending near the tip of the runner vane is convex toward the front surface of the runner vane. The runner vane is formed in a shape meeting a condition expressed by: ρs
摘要翻译：在流道叶片的径向部分中的弯曲部分具有在流道叶片的尖端附近延伸的弯曲部分朝向流道叶片的前表面凸出。流道叶片形成为满足以下条件的形状：rhos

5. 发明授权

US07151706B2 CMIS semiconductor nonvolatile storage circuit 有权
标题翻译： CMIS半导体非易失性存储电路
公开(公告)号：US07151706B2
公开(公告)日：2006-12-19
申请号：US11153113
申请日：2005-06-15
申请人： Kazuyuki Nakamura
发明人： Kazuyuki Nakamura
IPC分类号： G11C8/00
CPC分类号： G11C14/00 , G11C16/0466
摘要： A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a predetermined potential, a second MIS transistor having a second gate coupled to the selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to the predetermined potential, and a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node, wherein the selection line is operative to supply a write potential that creates a lingering change in a threshold voltage of one of the first MIS transistor and the second MIS transistor.
摘要翻译：非易失性半导体存储器电路包括选择线，第一位线，第二位线，具有耦合到选择线的第一栅极的第一MIS晶体管，经由第一节点耦合到第一位线的第一漏极，以及耦合到预定电位的第一源极，具有耦合到选择线的第二栅极的第二MIS晶体管，经由第二节点耦合到第二位线的第二漏极和耦合到预定电位的第二源极，以及锁存电路耦合到所述第一节点和所述第二节点以响应于所述第一节点和所述第二节点之间的信号差存储数据，其中所述选择线可操作以提供写入电位，所述写入电位在所述第一节点和所述第二节点之一的阈值电压中产生延迟变化第一MIS晶体管和第二MIS晶体管。

6. 发明授权

US5982447A System and method for combining two data streams while maintaining the continuous phase throughout the combined data stream 失效
标题翻译：用于组合两个数据流的系统和方法，同时保持整个组合数据流中的连续阶段
公开(公告)号：US5982447A
公开(公告)日：1999-11-09
申请号：US763895
申请日：1996-12-11
申请人： Kazuyuki Nakamura
发明人： Kazuyuki Nakamura
IPC分类号： H04N5/92 , G10L19/02 , G11B20/10 , G11B27/02 , G11B27/031 , G11B27/034 , H03M7/30 , H04N5/04 , H04N5/60 , H04N5/85 , H04N7/52 , H04N9/806 , H04N19/00 , H04N19/423 , H04N19/426 , H04N9/475
CPC分类号： H04N21/2368 , G11B27/034 , H04N21/23424 , H04N21/242 , H04N21/4302 , H04N21/4341 , H04N21/44016 , H04N5/04 , H04N9/8063 , G11B2220/2562 , G11B2220/913 , H04N5/602 , H04N5/85
摘要： A system and method for a generating a data stream for encoding by combining data from a multiple of sources. In order to maintain a continuous phase in the combined data stream, any phase differentials between the data supplied from the multiple sources are eliminated upon combination of the source data. The phase differential between the data from any two different sources is eliminated by trimming data from one of the sources such that when the trimmed data is combined with the data from the other source the resulting combined stream has a continuous phase.
摘要翻译：一种用于通过组合来自多个源的数据来生成用于编码的数据流的系统和方法。为了维持组合数据流中的连续相位，在源数据组合时，从多个源提供的数据之间的任何相位差被消除。通过从一个源修剪数据来消除来自任何两个不同源的数据之间的相位差，使得当修剪数据与来自其他源的数据组合时，所得到的组合流具有连续相位。

7. 发明授权

US5955230A Electrophotographic photoreceptor having protective layer and method for forming images 失效
标题翻译：具有保护层的电子照相感光体和形成图像的方法
公开(公告)号：US5955230A
公开(公告)日：1999-09-21
申请号：US851316
申请日：1997-05-05
申请人： Takaaki Kimura , Fumio Ojima , Kazuyuki Nakamura , Hirofumi Nakamura
发明人： Takaaki Kimura , Fumio Ojima , Kazuyuki Nakamura , Hirofumi Nakamura
IPC分类号： G03G5/147 , G03G13/08
CPC分类号： G03G5/14791 , G03G5/14734 , G03G5/14786
摘要： An electrophotographic photoreceptor excellent in wear resistance and low in residual potential comprising a conductive support, and a photoconductive layer and a protective layer formed on the conductive support. The protective layer contains a finely divided metal oxide powder and a binder resin composed of a polymer containing an acrylate or a methacrylate having at least one silicon-containing functional group as a monomer component, the polymer being crosslinked with said silicon-containing functional group. Also disclosed is an image forming method using the electrophotographic photoreceptor.
摘要翻译：具有优异的耐电阻性和低残留电位的电子照相感光体，包括导电性支持体，以及形成在导电性支持体上的感光层和保护层。保护层含有细碎的金属氧化物粉末和由包含具有至少一个含硅官能团的丙烯酸酯或甲基丙烯酸酯作为单体成分的聚合物构成的粘合剂树脂，该聚合物与所述含硅官能团交联。还公开了使用电子照相感光体的图像形成方法。

8. 发明授权

US5917364A Bi-directional interface circuit of reduced signal alteration 失效
标题翻译：减少信号变化的双向接口电路
公开(公告)号：US5917364A
公开(公告)日：1999-06-29
申请号：US997664
申请日：1997-12-23
申请人： Kazuyuki Nakamura
发明人： Kazuyuki Nakamura
IPC分类号： H04L25/49 , H03K19/00 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/0008 , H03K19/00346
摘要： To provide a bi-directional interface circuit which can reduce the simultaneous switching noise and the power consumption even at transitions of the signal direction, a bi-directional interface circuit of the invention comprises: an encoder (10) for generating an output bit sequence in synchronous with a clock cycle of the bus lines, said output bit sequence being obtained by coding an original signal and a redundant bit so that signal alteration rate of the output bit sequence to a preceding bit sequence thereof is less than a half; a decoder (20) for decoding the input bit sequence into an original bit sequence; and bypass lines (3) for bypassing the input bit sequence to the encoder for enabling the encoder to refer to the input bit sequence as the preceding bit sequence when the LSI chip begins to transfer the original signal. By providing a first encoder for generating an intermediate bit sequence having less than half logic `1` bits, and a second encoder for switching bit logic when corresponding bit of the intermediate bit sequence is logic `1`, the signal delay of the bypassed input bit sequence can be reduced and I/O clock frequency is not restricted.
摘要翻译：为了提供双向接口电路，即使在信号方向的转变时也能够降低同时的开关噪声和功耗，本发明的双向接口电路包括：编码器（10），用于产生输出位序列与总线的时钟周期同步，所述输出比特序列是通过对原始信号和冗余比特进行编码而获得的，使得输出比特序列的信号改变率与其前一比特序列小于一半; 解码器（20），用于将输入比特序列解码为原始比特序列; 以及用于将输入比特序列旁路到编码器的旁路线路（3），以便当LSI芯片开始传送原始信号时，使编码器能够将输入比特序列参考为前一比特序列。通过提供用于产生具有小于一半逻辑'1'比特的中间比特序列的第一编码器和用于在中间比特序列的对应比特为逻辑'1'时切换比特逻辑的第二编码器，旁路输入的信号延迟可以减少位序列，并且I / O时钟频率不受限制。

9. 发明授权

US5537543A Electronic mail drive type computer system and file operation method having a mail terminal operating independently of a computer system connected thereto 失效
标题翻译：电子邮件驱动型计算机系统和文件操作方法，其具有独立于连接到其的计算机系统工作的邮件终端
公开(公告)号：US5537543A
公开(公告)日：1996-07-16
申请号：US149553
申请日：1993-11-09
申请人： Tutomo Itoh , Toshio Hirosawa , Motohide Kokunishi , Atsushi Ueoka , Fujio Fujita , Yoshikazu Ichikawa , Tadashi Yamagishi , Masahiko Ishimaru , Hideki Namba , Kazuyuki Nakamura , Michio Hirano , Kaoru Kozuma , Shigeru Sasaki
发明人： Tutomo Itoh , Toshio Hirosawa , Motohide Kokunishi , Atsushi Ueoka , Fujio Fujita , Yoshikazu Ichikawa , Tadashi Yamagishi , Masahiko Ishimaru , Hideki Namba , Kazuyuki Nakamura , Michio Hirano , Kaoru Kozuma , Shigeru Sasaki
IPC分类号： H04L12/58 , G06F15/16
CPC分类号： H04L51/18 , G06F2209/549 , H04L51/30
摘要： In an arrangement of a mail terminal 1, an electronic mail system 2, a job control terminal 4, and a computer system 3, a user makes a proposal of a file operation via a mail by way of the mail terminal 1. The electronic mail system 2 stores therein the proposal mail, exchanges this proposal mail with the job control terminal 4, and furthermore distributes a file operation result to the respective mail terminals. The job control terminal 4 receives a mail from the electronic mail system 2, and interprets the proposal mail, thereby executing a conversion from a mail ID into a host ID, a judgement of an access authorization with respect to the designated file, and a production of an instruction to the computer process system 3. Furthermore, an execution host computer is selected by monitoring operation conditions of the host computers. When the file operation result is sent from the computer process system 3, a mail containing this file operation result is produced, and the resultant mail is sent to the electronic mail system 2. The computer system 3 interprets a command issued from the job control terminal 4, thereby executing a reading operation from the designated file, a writing operation to the designated file, and a reading operation of a file name list.
摘要翻译：在邮件终端1，电子邮件系统2，作业控制终端4和计算机系统3的布置中，用户通过邮件终端1通过邮件提出文件操作的提案。电子邮件系统2在其中存储提案邮件，与作业控制终端4交换该提案邮件，并且还将文件操作结果分配给各个邮件终端。作业控制终端4从电子邮件系统2接收邮件，解释提案邮件，从而执行从邮件ID到主机ID的转换，关于指定文件的访问授权的判断以及生产另外，通过监视主计算机的操作条件来选择执行主机计算机。当从计算机处理系统3发送文件操作结果时，产生包含该文件操作结果的邮件，并将所得到的邮件发送到电子邮件系统2.计算机系统3解释从作业控制终端发出的命令从而执行从指定文件的读取操作，对指定文件的写入操作和文件名称列表的读取操作。

10. 发明授权

US5463580A Static semiconductor memory device having improved read operation margin and speed 失效
标题翻译：具有改善的读取操作余量和速度的静态半导体存储器件
公开(公告)号：US5463580A
公开(公告)日：1995-10-31
申请号：US271663
申请日：1994-07-07
申请人： Kazuyuki Nakamura
发明人： Kazuyuki Nakamura
IPC分类号： G11C7/12 , G11C11/417 , G11C13/00
CPC分类号： G11C7/12 , G11C11/417
摘要： In a semiconductor memory device including a plurality of word lines, a plurality of pairs of bit lines, a plurality of static memory cells, at intersections between the word lines and the pairs of bit lines, and at least one sense amplifier for sensing a difference in potential between a selected pair of bit lines, a resistive load is connected to a substantial center location of each of the bit lines.
摘要翻译：在包括多个字线的半导体存储器件中，在字线和位线对之间的交叉处的多对位线，多个静态存储器单元以及用于感测差异的至少一个读出放大器在所选择的一对位线之间的电位中，电阻性负载连接到每个位线的实质中心位置。

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