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1. 发明授权

US06233663B1 Memory exclusive control device and method therefor 失效
标题翻译：内存独占控制装置及其方法
公开(公告)号：US06233663B1
公开(公告)日：2001-05-15
申请号：US09049108
申请日：1998-03-27
申请人： Kazushi Yamamoto , Yoshiyuki Iwamura , Toshinori Maeda , Toru Kakiage
发明人： Kazushi Yamamoto , Yoshiyuki Iwamura , Toshinori Maeda , Toru Kakiage
IPC分类号： G06F1202
CPC分类号： G06F13/1663
摘要： In the memory exclusive control device having a CPU-1 accessible to both a common memory and first memory devices, the CPU-1 is prohibited from accessing to the common memory device (105) during OFF state of an access permission flag, and when the access permissive flag ON is established by TCS (111), the gate of the access permitting unit (103) is opened to thereby permit the CPU-1 to access to the common memory device (105). Thus, the memory exclusive control can be realized for transferring a desired program to be processed to the address space of the first memory device, allowing omission of a third memory device.
摘要翻译：在具有公共存储器和第一存储器件可访问的CPU-1的存储器独占控制装置中，在访问许可标志的OFF状态期间禁止CPU-1访问公共存储器件（105），并且当访问许可标志ON由TCS（111）建立，访问许可单元（103）的门被打开，从而允许CPU-1访问公用存储设备（105）。因此，可以实现存储器排他控制以将要处理的期望程序传送到第一存储器件的地址空间，从而允许省略第三存储器件。

2. 发明申请

US20060069977A1 Error correction device 审中-公开
公开(公告)号：US20060069977A1
公开(公告)日：2006-03-30
申请号：US11221346
申请日：2005-09-08
申请人： Toshinori Maeda , Toru Kakiage
发明人： Toshinori Maeda , Toru Kakiage
IPC分类号： H03M13/00
CPC分类号： G11B20/18
摘要： In order to reduce the time required for error correction in the error correction device, data are transferred from the buffer memory not only to the syndrome calculator but also to the error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. In the error detection after the error corrector corrects the error, the mid-term results of the error detection obtained before the error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making it possible to execute error detection process at a halfway point.

3. 发明授权

US06986095B2 Error correction device 失效
标题翻译：纠错装置
公开(公告)号：US06986095B2
公开(公告)日：2006-01-10
申请号：US09848218
申请日：2001-05-04
申请人： Toshinori Maeda , Toru Kakiage
发明人： Toshinori Maeda , Toru Kakiage
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G11B20/18
摘要： For reducing time required for error correction in an error correction device, data are transferred from a buffer memory not only to a syndrome calculator but also to an error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. During error detection after the error corrector corrects the error, mid-term results of the error detection obtained before an error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making execution of an error detection process possible at a halfway point.
摘要翻译：为了减少误差校正装置中纠错所需的时间，数据不仅从缓冲存储器传送到校正子计数器，而且同时传送到错误检测器，直到校正子计算器检测到含错误代码，误差检测器与综合征计算器进行的综合征计算并行执行错误检测。在错误校正器纠正误差之后的错误检测期间，使用在检测到含错误代码之前获得的错误检测的中期结果。因此，不需要将所有数据从缓冲存储器传送到错误检测器，从而可以在中途执行错误检测处理。

4. 发明授权

US5548249A Clock generator and method for generating a clock 失效
标题翻译：时钟发生器和用于产生时钟的方法
公开(公告)号：US5548249A
公开(公告)日：1996-08-20
申请号：US443577
申请日：1995-05-17
申请人： Masaya Sumita , Toshinori Maeda , Toru Kakiage
发明人： Masaya Sumita , Toshinori Maeda , Toru Kakiage
IPC分类号： H03L7/14 , H03L7/183 , H03L7/08 , H03L7/16
CPC分类号： H03L7/14 , H03L7/183
摘要： The clock generator of this invention includes: an input shutoff control circuit for receiving a base clock and a reference clock and outputting a first signal and a second signal in response to a reset signal, a phase comparator for outputting a phase difference signal indicating a phase difference between the first signal and the second signal; a voltage control oscillator for outputting a frequency variable clock in correspondence with the phase difference signal; and a voltage fixing control circuit for controlling a voltage of the phase difference signal in response to the reset signal, wherein, when the reset signal is in a first level, the input shutoff control circuit: outputs the base clock to the phase comparator as the first signal and outputs the reference clock to the phase comparator as the second signal, and the voltage fixing control circuit holds the voltage of the phase difference signal, and when the reset signal is in a second level different from the first level, the input shutoff control circuit outputs two signals to the phase comparator as the first signal and the second signal, the phase difference between the two signals being substantially zero, and the voltage fixing control circuit fixing the voltage of the phase difference signal to a predetermined voltage at which the voltage control oscillator does not oscillate.
摘要翻译：本发明的时钟发生器包括：输入切断控制电路，用于接收基准时钟和参考时钟，并响应复位信号输出第一信号和第二信号;相位比较器，用于输出指示相位的相位差信号第一信号和第二信号之间的差; 电压控制振荡器，用于输出与所述相位差信号相对应的频率可变时钟; 以及电压固定控制电路，用于响应于所述复位信号来控制所述相位差信号的电压，其中，当所述复位信号处于第一电平时，所述输入关断控制电路将所述基准时钟输出到所述相位比较器第一信号并将参考时钟作为第二信号输出到相位比较器，并且电压固定控制电路保持相位差信号的电压，并且当复位信号处于与第一电平不同的第二电平时，输入关断控制电路将作为第一信号和第二信号的两个信号输出到相位比较器，两个信号之间的相位差基本为零，并且电压固定控制电路将相位差信号的电压固定为预定电压，电压控制振荡器不振荡。

5. 发明授权

US6041368A System for operating input, processing and output units in parallel and using DMA circuit for successively transferring data through the three units via an internal memory 失效
标题翻译：用于并行操作输入，处理和输出单元的系统，并使用DMA电路，通过内部存储器连续传输三个单元的数据
公开(公告)号：US6041368A
公开(公告)日：2000-03-21
申请号：US053966
申请日：1998-04-02
申请人： Fumio Nakatsuji , Toshinori Maeda , Hiroshi Kamiyama
发明人： Fumio Nakatsuji , Toshinori Maeda , Hiroshi Kamiyama
IPC分类号： G06F11/10 , G11B20/10 , G06F13/14
CPC分类号： G06F11/1008 , G11B20/10527
摘要： A data input-output device includes a single memory, an input interface unit for storing data in the memory, an operation unit for fetching the data from the memory, for performing operations on the data, and for updating the data in the memory when necessary, an output interface unit for transmitting the data in the memory that has been operated on by the operation unit to outside of the device, and a bus control unit for setting a priority for each of these units and for controlling memory access by these units according to the priorities every time a predetermined number of bytes of data is transferred.
摘要翻译：数据输入输出装置包括单个存储器，用于在存储器中存储数据的输入接口单元，用于从存储器取出数据的操作单元，用于对数据进行操作，以及在需要时更新存储器中的数据输出接口单元，用于将已经由操作单元操作的存储器中的数据发送到设备外部;以及总线控制单元，用于为这些单元中的每一个设置优先级，并且用于控制这些单元的存储器访问，每次传输预定数量的字节数据时，都可以使用优先级。

6. 发明授权

US5349671A Microprocessor system generating instruction fetch addresses at high speed 失效
标题翻译：微处理器系统以高速生成指令提取地址
公开(公告)号：US5349671A
公开(公告)日：1994-09-20
申请号：US494368
申请日：1990-03-16
申请人： Toshinori Maeda , Tomoharu Kawada , Jiro Miyake
发明人： Toshinori Maeda , Tomoharu Kawada , Jiro Miyake
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/30094 , G06F9/30058 , G06F9/30072
摘要： A microprocessor system which comprises an arithmetic logic unit for generating flags, a flag update detector for outputting a flag update detecting signal, a status register coupled to the flag update detector and the arithmetic logic unit for receiving the flag update detecting signal and a flag outputted from the arithmetic logic unit, a first address outputting portion coupled to the flag update detector and the status register for receiving the flag update detecting signal, a flag outputted from the status register, a target instruction address, a next instruction address and a branch condition for determining according to the flag received from the status register whether or not the branch condition is met, and for outputting first and second address candidates selected from the target instruction address and the next instruction address according to the flag update signal and to whether or not the branch condition is met, and a second address outputting portion coupled to the first address outputting portion and the arithmetic logic unit for receiving the first and second address candidates outputted from the first address outputting portion, the branch condition and the flag outputted from the arithmetic logic unit, for determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met, and for outputting the target instruction address or the next instruction address as an instruction fetch address on the basis of a result of determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met.
摘要翻译：一种微处理器系统，包括用于产生标志的算术逻辑单元，用于输出标志更新检测信号的标志更新检测器，耦合到标志更新检测器的状态寄存器和用于接收标志更新检测信号的运算逻辑单元和输出的标志来自算术逻辑单元的第一地址输出部分耦合到标志更新检测器和用于接收标志更新检测信号的状态寄存器，从状态寄存器输出的标志，目标指令地址，下一个指令地址和分支条件用于根据从状态寄存器接收到的标志来确定是否满足分支条件，并且根据标志更新信号输出从目标指令地址和下一个指令地址中选择的第一和第二地址候选以及是否满足分支条件，并且耦合到fi的第二地址输出部分第一地址输出部分和用于接收从第一地址输出部分输出的第一和第二地址候选的运算逻辑单元，从算术逻辑单元输出的分支条件和标志，用于根据从算术逻辑单元接收的标志是否满足分支条件，并且基于根据从算术逻辑单元接收到的标志的确定结果，输出目标指令地址或下一个指令地址作为指令获取地址，分支条件遇到了

7. 发明授权

US06697989B1 Method and apparatus for error correction 失效
标题翻译：纠错方法和装置
公开(公告)号：US06697989B1
公开(公告)日：2004-02-24
申请号：US09657779
申请日：2000-09-08
申请人： Toshinori Maeda , Yukio Iijima
发明人： Toshinori Maeda , Yukio Iijima
IPC分类号： H03M1300
CPC分类号： H03M13/2909 , G11B20/1833 , G11B20/1866 , G11B2020/1853 , G11B2220/2562 , H03M13/3715 , H03M13/6325
摘要： The present invention provides an error correction apparatus and an error correction method, which does not execute unnecessary syndrome operation and operation processing subsequent to the syndrome operation. A format interface 10a judges whether an uncorrectable error is included in parallel with demodulation of received data, and outputs an error correction incapability detection signal when the uncorrectable error is included. The error correction circuit 20a executes decoding of the error correction, including syndrome operation, for demodulated data from the format interface 10a, suspends the syndrome operation when the error correction incapability detection signal is input, and terminates the error correction.
摘要翻译：本发明提供了一种纠错装置和纠错方法，其不执行在综合征操作之后的不必要的综合症状操作和操作处理。格式接口10a判断是否与接收数据的解调并行地包括不可校正的错误，并且当包括不可校正的错误时，输出纠错不能检测信号。误差校正电路20a对来自格式化接口10a的解调数据执行纠错操作的纠错解码，在错误校正无效检测信号被输入时暂停该校正子操作，并终止纠错。

8. 发明授权

US3935349A Process of coating an aluminum article 失效
标题翻译：涂铝件的工艺
公开(公告)号：US3935349A
公开(公告)日：1976-01-27
申请号：US402364
申请日：1973-10-01
申请人： Shiro Terai , Akinari Ichiryu , Toshio Suzuki , Toshinori Maeda
发明人： Shiro Terai , Akinari Ichiryu , Toshio Suzuki , Toshinori Maeda
IPC分类号： B05D1/18 , B05D3/10 , B05D7/00 , B05D7/14 , B05D7/16 , C23C22/00 , C23C22/83 , C25D11/24 , C23F7/06
CPC分类号： B05D7/14 , C23C22/83 , C25D11/24 , B05D1/185 , B05D2202/25 , B05D3/102 , B05D7/52
摘要： A paint film based on a thermo-setting resin which is applied on an aluminum article may be improved in its adhesion properties and resistance to chemical and mechanical attacks as well as in its resistance to weathering, if the surface of the aluminum article is previously anodized to form the oxide surface layer or is treated in boiling water to form the boehmite surface layer and if the oxide surface layer, including the boehmite layer, is pre-treated with a silane compound prior to the application of the coating composition. The application of the paint composition is conducted in this invention by means of a known coating technique such as dipping, spraying, showering, brushing or roller-coating, other than the electro-deposition technique.
摘要翻译：如果将铝制品的表面预先阳极氧化，则涂敷在铝制品上的基于热固树脂的漆膜可以改善其粘合性能和抗化学和机械性能以及耐候性形成氧化物表面层，或在沸水中处理以形成勃姆石表面层，并且如果包含勃姆石层的氧化物表面层在施加涂料组合物之前用硅烷化合物预处理。涂料组合物的应用通过除电沉积技术以外的已知的涂覆技术如浸渍，喷涂，淋洗，刷涂或辊涂等方法在本发明中进行。

9. 发明授权

US07739571B2 Semiconductor integrated circuit and system LSI having a test expected value programming circuit 失效
标题翻译：具有测试期望值编程电路的半导体集成电路和系统LSI
公开(公告)号：US07739571B2
公开(公告)日：2010-06-15
申请号：US11795904
申请日：2005-09-27
申请人： Yasuteru Maeda , Toshinori Maeda
发明人： Yasuteru Maeda , Toshinori Maeda
IPC分类号： G06F11/27 , G06F11/25 , G06F11/263
CPC分类号： G01R31/318594 , G01R31/31713 , G01R31/3172
摘要： In a semiconductor integrated circuit 11, there is constructed a test expected value programming circuit 100 having an input/input-output pad 103 for retrieving a ground/power-source signal 104 from a ground terminal 30 or a power source terminal 31 connected to the semiconductor integrated circuit 11, a switch 105 for selectively switching the outputting of the ground/power-source signal 104 inputted via the input/input-output pad 103, and an expected value generation circuit 13 for generating a test expected value signal 21 based on a switch output signal 122 outputted from the switch 105.
摘要翻译：在半导体集成电路11中，构成了具有输入/输入 - 输出焊盘103的测试期望值编程电路100，用于从接地端子30或与其连接的电源端子31检索接地/电源信号104 半导体集成电路11，用于选择性地切换经由输入/输入 - 输出焊盘103输入的接地/电源信号104的输出的开关105，以及用于产生测试期望值信号21的期望值产生电路13，基于从开关105输出的开关输出信号122。

10. 发明申请

US20080141089A1 Semiconductor Integrated Circuit and System Lsi 失效
标题翻译：半导体集成电路与系统
公开(公告)号：US20080141089A1
公开(公告)日：2008-06-12
申请号：US11795904
申请日：2005-09-27
申请人： Yasuteru Maeda , Toshinori Maeda
发明人： Yasuteru Maeda , Toshinori Maeda
IPC分类号： G06F11/27 , G06F11/25 , G06F11/263
CPC分类号： G01R31/318594 , G01R31/31713 , G01R31/3172
摘要： In a semiconductor integrated circuit 11, there is constructed a test expected value programming circuit 100 having an input/input-output pad 103 for retrieving a ground/power-source signal 104 from a ground terminal 30 or a power source terminal 31 connected to the semiconductor integrated circuit 11, a switch 105 for selectively switching the outputting of the ground/power-source signal 104 inputted via the input/input-output pad 103, and an expected value generation circuit 13 for generating a test expected value signal 21 based on a switch output signal 122 outputted from the switch 105.
摘要翻译：在半导体集成电路11中，构成了具有输入/输入 - 输出焊盘103的测试期望值编程电路100，用于从接地端子30或与其连接的电源端子31检索接地/电源信号104 半导体集成电路11，用于选择性地切换经由输入/输入 - 输出焊盘103输入的接地/电源信号104的输出的开关105，以及用于产生测试期望值信号21的期望值产生电路13，基于从开关105输出的开关输出信号122。

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