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1. 发明申请

US20130111254A1 Multi-Path Power Switch Scheme for Functional Block Wakeup 有权
标题翻译：功能块唤醒的多路径电源开关方案
公开(公告)号：US20130111254A1
公开(公告)日：2013-05-02
申请号：US13285294
申请日：2011-10-31
申请人： Toshinari Takayanagi , Shingo Suzuki
发明人： Toshinari Takayanagi , Shingo Suzuki
IPC分类号： G06F1/12
CPC分类号： G06F1/189 , G06F1/26
摘要： A multi-path power switch scheme for functional block wakeup is disclosed. The scheme may be applied to functional blocks of an integrated circuit. When a power on procedure is initiated within a given functional block, a first group of power switches in a functional block may be powered on, while a second group of power switches is inhibited from powering on. After a predetermined time has elapsed, activation of the second group of power switches is initiated. After initiation of a power up procedure for a given functional block, the powering up of a second functional block to be powered on may initially be inhibited. After a predetermined time has elapsed, the powering on of the second functional block may be initiated. Overlap between times when the first and second groups of switches are active may depend on process, voltage, and temperature variations.
摘要翻译：公开了用于功能块唤醒的多路径功率开关方案。该方案可以应用于集成电路的功能块。当在给定功能块内启动通电过程时，功能块中的第一组电源开关可以被接通，而第二组电源开关被禁止上电。在经过预定时间之后，启动第二组电源开关。在对给定的功能块启动加电程序之后，可以初始地禁止上电的第二功能块的上电。在经过预定时间之后，可启动第二功能块的上电。当第一组和第二组开关处于活动状态时，重叠可能取决于过程，电压和温度变化。

2. 发明申请

US20130106494A1 Power Switch Acceleration Scheme for Fast Wakeup 有权
标题翻译：用于快速唤醒的电源开关加速方案
公开(公告)号：US20130106494A1
公开(公告)日：2013-05-02
申请号：US13285269
申请日：2011-10-31
申请人： Toshinari Takayanagi , Shingo Suzuki
发明人： Toshinari Takayanagi , Shingo Suzuki
IPC分类号： H03K17/687
CPC分类号： H03K17/284 , H03K17/0412 , H03K17/04206 , H03K17/164 , H03K19/0016 , H03K19/00361 , Y10T307/858
摘要： A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.
摘要翻译：公开了一种在唤醒期间用于电源开关加速方案的装置。在一个实施例中，集成电路包括至少一个电源门控电路块。电源门控电路块包括一个虚拟电压节点，当有效时，电压被提供给块的电路。电源开关耦合在虚拟电压节点和相应的全局电压节点之间。当电源门控电路块通电时，电源开关被顺序激活。电源开关激活的速率随着虚拟电压节点上的电压的增加而增加。顺序地激活功率开关可以防止电流涌入电源门控电路块中的过多电流。当虚拟电压节点上的电压至少处于一定水平时，功率开关被激活的速率的增加可以允许更快的唤醒。

3. 发明授权

US08362805B2 Power switch ramp rate control using daisy-chained flops 有权
标题翻译：电源开关斜坡率控制使用菊花链触发器
公开(公告)号：US08362805B2
公开(公告)日：2013-01-29
申请号：US12705834
申请日：2010-02-15
申请人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
发明人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
IPC分类号： H03K193/00 , H03B21/00
CPC分类号： H03K19/0016 , Y10T307/766
摘要： In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.
摘要翻译：在一个实施例中，集成电路可以包括一个或多个功率管理块和功率管理器电路。功率管理器电路可以被配置为为每个功率管理块和块使能时钟生成块使能。功率管理块可以在功率管理块中产生各种功率开关的本地块使能，交错块启用超过两个或更多个块使能时钟周期。特别地，功率管理块可以包括从功率管理器电路接收块使能的一组串联的触发器。每个触发器的输出可以耦合到相应的一组电源开关，并且可以启用这些开关。因此可以控制由于使能和/或禁用功率管理块而引起的电流流动的变化。在一个实施例中，块使能时钟的频率可以被设置为独立于集成电路中的处理，电压和温度条件的限定值。

4. 发明授权

US08120208B2 Impedance-based power supply switch optimization 有权
标题翻译：基于阻抗的电源开关优化
公开(公告)号：US08120208B2
公开(公告)日：2012-02-21
申请号：US12484692
申请日：2009-06-15
申请人： Toshinari Takayanagi , Shingo Suzuki
发明人： Toshinari Takayanagi , Shingo Suzuki
IPC分类号： G05F1/10
CPC分类号： G06F1/26 , Y10T307/74 , Y10T307/747
摘要： In one embodiment, a power gated circuit block includes power switches that couple at least one of the power supply grids within the block to the global power supply grids of the integrated circuit. The power switches receive an enable that indicates whether or not the power gated block is enabled or disabled. If the power gated block is enabled, the power switches are turned on and electrically connect the global power supply grid with the internal (or local) power supply grid; otherwise the power switches electrically isolate the local power supply grid from the global power supply grid. The power switches are physically distributed over an area occupied by the power gated block, including near an edge of the area. The number of power switches near the edge is greater than the number of switches included at other locations in the area to provide a worst case impedance experienced at points throughout the area that is approximately equal.
摘要翻译：在一个实施例中，功率门控电路块包括将块内的电源栅格中的至少一个耦合到集成电路的全局电源栅极的功率开关。电源开关接收到指示电源门控块是否被使能或禁用的使能。如果启用电源门控功能，则电源开关打开，并将全局电源网格与内部（或本地）电源网格电连接; 否则电源开关将本地电源网与全球电源网电隔离。功率开关物理分布在由电力门控块占据的区域上，包括该区域的边缘附近。靠近边缘的功率开关的数量大于包括在该区域中的其它位置处的开关的数量，以提供在大致相等的区域处经历的最差情况阻抗。

5. 发明申请

US20110198942A1 Power Switch Ramp Rate Control Using Programmable Connection to Switches 有权
标题翻译：使用可编程连接到开关的电源开关斜坡率控制
公开(公告)号：US20110198942A1
公开(公告)日：2011-08-18
申请号：US12705837
申请日：2010-02-15
申请人： Toshinari Takayanagi , Shingo Suzuki , Jung-Cheng Yeh , Conrad H. Ziesler
发明人： Toshinari Takayanagi , Shingo Suzuki , Jung-Cheng Yeh , Conrad H. Ziesler
IPC分类号： H01H35/00
CPC分类号： H03K19/0016 , Y10T307/766
摘要： In an embodiment, an integrated circuit includes a power gated block and a power manager circuit. The power manager circuit is configured to provide a block enable signal and at least one select signal to the power gated block. The power manager may generate the select signal responsive to various parameters that affect the speed of the integrated circuit, such as power supply voltage magnitude, operating temperature, and/or process corner. The power gated block may control the rate at which power switches are enabled based on the select signal or signals. For example, the power switches may be enabled in a more parallel or more serial fashion and/or the drive strength of block enable buffering to the power switches may be varied. In another embodiment, the power manager circuit may assert multiple block enables to the power gated block (which are connected to separate sets of power switches), and may control the timing of assertion of the enables to control the rate at which power switches are enabled.
摘要翻译：在一个实施例中，集成电路包括电源门控块和功率管理器电路。功率管理器电路被配置为向电源门控块提供块使能信号和至少一个选择信号。功率管理器可以响应于影响集成电路的速度的各种参数（例如电源电压幅度，工作温度和/或过程角）来产生选择信号。电源门控块可以基于选择信号或信号来控制使能电源开关的速率。例如，功率开关可以以更并行或更串联的方式启用和/或可以改变对功率开关的块使能缓冲的驱动强度。在另一个实施例中，功率管理器电路可以将功率门控块（其连接到单独的功率开关组）断言多个块使能，并且可以控制用于控制功率开关被使能的速率的使能的定时。

6. 发明申请

US20110198941A1 Power Switch Ramp Rate Control Using Daisy-Chained Flops 有权
标题翻译：电源开关斜坡速率控制使用菊花链触发器
公开(公告)号：US20110198941A1
公开(公告)日：2011-08-18
申请号：US12705834
申请日：2010-02-15
申请人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
发明人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
IPC分类号： H01H35/00
CPC分类号： H03K19/0016 , Y10T307/766
摘要： In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.
摘要翻译：在一个实施例中，集成电路可以包括一个或多个功率管理块和功率管理器电路。功率管理器电路可以被配置为为每个功率管理块和块使能时钟生成块使能。功率管理块可以在功率管理块中产生各种功率开关的本地块使能，交错块启用超过两个或更多个块使能时钟周期。特别地，功率管理块可以包括从功率管理器电路接收块使能的一组串联的触发器。每个触发器的输出可以耦合到相应的一组电源开关，并且可以启用这些开关。因此可以控制由于使能和/或禁用功率管理块而引起的电流流动的变化。在一个实施例中，块使能时钟的频率可以被设置为独立于集成电路中的处理，电压和温度条件的限定值。

7. 发明申请

US20100314948A1 Impedance-Based Power Supply Switch Optimization 有权
标题翻译：基于阻抗的电源开关优化
公开(公告)号：US20100314948A1
公开(公告)日：2010-12-16
申请号：US12484692
申请日：2009-06-15
申请人： Toshinari Takayanagi , Shingo Suzuki
发明人： Toshinari Takayanagi , Shingo Suzuki
IPC分类号： G05F1/10
CPC分类号： G06F1/26 , Y10T307/74 , Y10T307/747
摘要： In one embodiment, a power gated circuit block includes power switches that couple at least one of the power supply grids within the block to the global power supply grids of the integrated circuit. The power switches receive an enable that indicates whether or not the power gated block is enabled or disabled. If the power gated block is enabled, the power switches are turned on and electrically connect the global power supply grid with the internal (or local) power supply grid; otherwise the power switches electrically isolate the local power supply grid from the global power supply grid. The power switches are physically distributed over an area occupied by the power gated block, including near an edge of the area. The number of power switches near the edge is greater than the number of switches included at other locations in the area to provide a worst case impedance experienced at points throughout the area that is approximately equal.
摘要翻译：在一个实施例中，功率门控电路块包括将块内的电源栅格中的至少一个耦合到集成电路的全局电源栅极的功率开关。电源开关接收到指示电源门控块是否被使能或禁用的使能。如果启用电源门控功能，则电源开关打开，并将全局电源网格与内部（或本地）电源网格电连接; 否则电源开关将本地电源网与全球电源网电隔离。功率开关物理分布在由电力门控块占据的区域上，包括该区域的边缘附近。靠近边缘的功率开关的数量大于包括在该区域中的其它位置处的开关的数量，以提供在大致相等的区域处经历的最差情况阻抗。

8. 发明授权

US08786309B2 Multi-path power switch scheme for functional block wakeup 有权
标题翻译：用于功能块唤醒的多路径电源开关方案
公开(公告)号：US08786309B2
公开(公告)日：2014-07-22
申请号：US13285294
申请日：2011-10-31
申请人： Toshinari Takayanagi , Shingo Suzuki
发明人： Toshinari Takayanagi , Shingo Suzuki
IPC分类号： H03K19/23 , H03K17/0412 , G06F1/18 , G06F1/26
CPC分类号： G06F1/189 , G06F1/26
摘要： A multi-path power switch scheme for functional block wakeup is disclosed. The scheme may be applied to functional blocks of an integrated circuit. When a power on procedure is initiated within a given functional block, a first group of power switches in a functional block may be powered on, while a second group of power switches is inhibited from powering on. After a predetermined time has elapsed, activation of the second group of power switches is initiated. After initiation of a power up procedure for a given functional block, the powering up of a second functional block to be powered on may initially be inhibited. After a predetermined time has elapsed, the powering on of the second functional block may be initiated. Overlap between times when the first and second groups of switches are active may depend on process, voltage, and temperature variations.
摘要翻译：公开了用于功能块唤醒的多路径功率开关方案。该方案可以应用于集成电路的功能块。当在给定功能块内启动通电过程时，功能块中的第一组电源开关可以被接通，而第二组电源开关被禁止上电。在经过预定时间之后，启动第二组电源开关。在对给定的功能块启动加电过程之后，可以初始地抑制要加电的第二功能块的上电。在经过预定时间之后，可启动第二功能块的上电。当第一组和第二组开关处于活动状态时，重叠可能取决于过程，电压和温度变化。

9. 发明授权

US08542054B2 Power switch acceleration scheme for fast wakeup 有权
标题翻译：电源开关加速方案快速唤醒
公开(公告)号：US08542054B2
公开(公告)日：2013-09-24
申请号：US13285269
申请日：2011-10-31
申请人： Toshinari Takayanagi , Shingo Suzuki
发明人： Toshinari Takayanagi , Shingo Suzuki
IPC分类号： H03K17/296
CPC分类号： H03K17/284 , H03K17/0412 , H03K17/04206 , H03K17/164 , H03K19/0016 , H03K19/00361 , Y10T307/858
摘要： A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.
摘要翻译：公开了一种在唤醒期间用于电源开关加速方案的装置。在一个实施例中，集成电路包括至少一个电源门控电路块。电源门控电路块包括一个虚拟电压节点，当有效时，电压被提供给块的电路。电源开关耦合在虚拟电压节点和相应的全局电压节点之间。当电源门控电路块通电时，电源开关被顺序激活。电源开关激活的速率随着虚拟电压节点上的电压的增加而增加。顺序地激活功率开关可以防止电流涌入电源门控电路块中的过多电流。当虚拟电压节点上的电压至少处于一定水平时，功率开关被激活的速率的增加可以允许更快的唤醒。

10. 发明授权

US08421499B2 Power switch ramp rate control using programmable connection to switches 有权
标题翻译：电源开关斜坡率控制使用可编程连接到开关
公开(公告)号：US08421499B2
公开(公告)日：2013-04-16
申请号：US12705837
申请日：2010-02-15
申请人： Toshinari Takayanagi , Shingo Suzuki , Jung-Cheng Yeh , Conrad H. Ziesler
发明人： Toshinari Takayanagi , Shingo Suzuki , Jung-Cheng Yeh , Conrad H. Ziesler
IPC分类号： H03K19/23
CPC分类号： H03K19/0016 , Y10T307/766
摘要： In an embodiment, an integrated circuit includes a power gated block and a power manager circuit. The power manager circuit is configured to provide a block enable signal and at least one select signal to the power gated block. The power manager may generate the select signal responsive to various parameters that affect the speed of the integrated circuit, such as power supply voltage magnitude, operating temperature, and/or process corner. The power gated block may control the rate at which power switches are enabled based on the select signal or signals. For example, the power switches may be enabled in a more parallel or more serial fashion and/or the drive strength of block enable buffering to the power switches may be varied. In another embodiment, the power manager circuit may assert multiple block enables to the power gated block (which are connected to separate sets of power switches), and may control the timing of assertion of the enables to control the rate at which power switches are enabled.
摘要翻译：在一个实施例中，集成电路包括电源门控块和功率管理器电路。功率管理器电路被配置为向电源门控块提供块使能信号和至少一个选择信号。功率管理器可以响应于影响集成电路的速度的各种参数（例如电源电压幅度，工作温度和/或过程角）来产生选择信号。电源门控块可以基于选择信号或信号来控制使能电源开关的速率。例如，功率开关可以以更并行或更串联的方式启用和/或可以改变对功率开关的块使能缓冲的驱动强度。在另一实施例中，功率管理器电路可以将功率门控块（其连接到单独的功率开关组）断言多个块使能，并且可以控制用于控制功率开关被使能的速率的使能的定时。

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