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1. 发明授权

US08362805B2 Power switch ramp rate control using daisy-chained flops 有权
标题翻译：电源开关斜坡率控制使用菊花链触发器
公开(公告)号：US08362805B2
公开(公告)日：2013-01-29
申请号：US12705834
申请日：2010-02-15
申请人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
发明人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
IPC分类号： H03K193/00 , H03B21/00
CPC分类号： H03K19/0016 , Y10T307/766
摘要： In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.
摘要翻译：在一个实施例中，集成电路可以包括一个或多个功率管理块和功率管理器电路。功率管理器电路可以被配置为为每个功率管理块和块使能时钟生成块使能。功率管理块可以在功率管理块中产生各种功率开关的本地块使能，交错块启用超过两个或更多个块使能时钟周期。特别地，功率管理块可以包括从功率管理器电路接收块使能的一组串联的触发器。每个触发器的输出可以耦合到相应的一组电源开关，并且可以启用这些开关。因此可以控制由于使能和/或禁用功率管理块而引起的电流流动的变化。在一个实施例中，块使能时钟的频率可以被设置为独立于集成电路中的处理，电压和温度条件的限定值。

2. 发明申请

US20110198941A1 Power Switch Ramp Rate Control Using Daisy-Chained Flops 有权
标题翻译：电源开关斜坡速率控制使用菊花链触发器
公开(公告)号：US20110198941A1
公开(公告)日：2011-08-18
申请号：US12705834
申请日：2010-02-15
申请人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
发明人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
IPC分类号： H01H35/00
CPC分类号： H03K19/0016 , Y10T307/766
摘要： In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.
摘要翻译：在一个实施例中，集成电路可以包括一个或多个功率管理块和功率管理器电路。功率管理器电路可以被配置为为每个功率管理块和块使能时钟生成块使能。功率管理块可以在功率管理块中产生各种功率开关的本地块使能，交错块启用超过两个或更多个块使能时钟周期。特别地，功率管理块可以包括从功率管理器电路接收块使能的一组串联的触发器。每个触发器的输出可以耦合到相应的一组电源开关，并且可以启用这些开关。因此可以控制由于使能和/或禁用功率管理块而引起的电流流动的变化。在一个实施例中，块使能时钟的频率可以被设置为独立于集成电路中的处理，电压和温度条件的限定值。

3. 发明授权

US07355905B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
标题翻译：具有不同于逻辑电路电源电压的存储器的单独电源电压的集成电路
公开(公告)号：US07355905B2
公开(公告)日：2008-04-08
申请号：US11173565
申请日：2005-07-01
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供有在使用期间大于所述第一电源电压的第二电源电压。

4. 发明授权

US07760559B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
标题翻译：具有不同于逻辑电路电源电压的存储器的单独电源电压的集成电路
公开(公告)号：US07760559B2
公开(公告)日：2010-07-20
申请号：US12325476
申请日：2008-12-01
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

5. 发明授权

US08416635B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
公开(公告)号：US08416635B2
公开(公告)日：2013-04-09
申请号：US13617344
申请日：2012-09-14
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

6. 发明申请

US20130016575A1 Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage 有权
标题翻译：具有与逻辑电路电源电压不同的存储器的独立电源电压的集成电路
公开(公告)号：US20130016575A1
公开(公告)日：2013-01-17
申请号：US13617344
申请日：2012-09-14
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

7. 发明授权

US08098534B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
标题翻译：具有不同于逻辑电路电源电压的存储器的单独电源电压的集成电路
公开(公告)号：US08098534B2
公开(公告)日：2012-01-17
申请号：US12791080
申请日：2010-06-01
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供有在使用期间大于所述第一电源电压的第二电源电压。

8. 发明申请

US20110235442A1 Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage 有权
标题翻译：具有与逻辑电路电源电压不同的存储器的独立电源电压的集成电路
公开(公告)号：US20110235442A1
公开(公告)日：2011-09-29
申请号：US13155097
申请日：2011-06-07
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

9. 发明申请

US20100238745A1 Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage 有权
标题翻译：具有与逻辑电路电源电压不同的存储器的独立电源电压的集成电路
公开(公告)号：US20100238745A1
公开(公告)日：2010-09-23
申请号：US12791080
申请日：2010-06-01
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

10. 发明授权

US08289785B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
公开(公告)号：US08289785B2
公开(公告)日：2012-10-16
申请号：US13155097
申请日：2011-06-07
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

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