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1. 发明申请

US20130033899A1 REFLECTING BASE MATERIAL, BACKLIGHT UNIT, AND METHOD FOR MANUFACTURING REFLECTING BASE MATERIAL 审中-公开
标题翻译：反射基材，背光单元和制造反射基材的方法
公开(公告)号：US20130033899A1
公开(公告)日：2013-02-07
申请号：US13616875
申请日：2012-09-14
申请人： Toshimitsu Nishiwaki , Nobuyuki Morita , Akihiko Ishikawa , Motohiro Yamane , Daisuke Hayashi , Koichi Kawai , Yusuke Satoh
发明人： Toshimitsu Nishiwaki , Nobuyuki Morita , Akihiko Ishikawa , Motohiro Yamane , Daisuke Hayashi , Koichi Kawai , Yusuke Satoh
IPC分类号： F21V8/00 , B29D11/00 , G02B27/00
CPC分类号： G02B27/0977 , G02F1/133605 , G02F1/133611
摘要： A reflecting base material that can reliably prevent the occurrence of uneven brightness, a backlight unit that uses the same, and a method for manufacturing the same are provided. Surface profile information of the reflecting base material 7 is obtained by a laser displacement gauge 3. Next, the unevenness information obtained is subjected to Fourier transform, and the relationship between frequency and intensity for the surface unevenness profile of the reflecting base material is obtained. Next, the calculated relationship between the frequency and intensity is compared with a preset standard data. When the intensity exceeds 0.6 at a predetermined range of frequency domain, a judgment of rejection is made; when no data exceeding 0.6 exists in said judgment domain, a judgment of acceptance is made.
摘要翻译：提供了可以可靠地防止亮度不均的反射基材，使用其的背光单元及其制造方法。通过激光位移计3获得反射基材7的表面轮廓信息。接下来，对获得的不平坦信息进行傅里叶变换，得到反射基材的表面凹凸轮廓的频率与强度的关系。接下来，将计算的频率和强度之间的关系与预设的标准数据进行比较。当在频域的预定范围内的强度超过0.6时，进行拒绝判断; 当在所述判断域中不存在超过0.6的数据时，进行接受判断。

2. 发明申请

US20120327713A1 IN-FIELD BLOCK RETIRING 有权
标题翻译：现场块退火
公开(公告)号：US20120327713A1
公开(公告)日：2012-12-27
申请号：US13165416
申请日：2011-06-21
申请人： Krishna K. Parat , Akira Goda , Koichi Kawai , Brian J. Soderling , Jeremy Binfet , Arnaud A. Furnemont , Tejas Krishnamohan , Tyson M. Stichka , Giuseppina Puzzilli
发明人： Krishna K. Parat , Akira Goda , Koichi Kawai , Brian J. Soderling , Jeremy Binfet , Arnaud A. Furnemont , Tejas Krishnamohan , Tyson M. Stichka , Giuseppina Puzzilli
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C29/765 , G11C11/5628 , G11C16/0483 , G11C16/16 , G11C16/349 , G11C29/789
摘要： Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.
摘要翻译：公开了存储器件和方法，包括涉及擦除存储器单元块的方法。在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。如果坏字符串的数量超过阈值，则该块将从使用中退出。公开了另外的实施例。

3. 发明授权

US08218373B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
标题翻译：半导体集成电路适用于输出内部操作的通过/失败结果
公开(公告)号：US08218373B2
公开(公告)日：2012-07-10
申请号：US12981063
申请日：2010-12-29
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

4. 发明申请

US20090080264A1 SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS 有权
标题翻译：半导体集成电路适用于输出通过/内部运行失败的结果
公开(公告)号：US20090080264A1
公开(公告)日：2009-03-26
申请号：US12252896
申请日：2008-10-16
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/06 , G11C7/10 , G11C7/00
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

5. 发明授权

US07411830B2 Nonvolatile memory cell having current compensated for temperature dependency and data read method thereof 有权
标题翻译：具有电流补偿温度依赖性和数据读取方法的非易失性存储单元
公开(公告)号：US07411830B2
公开(公告)日：2008-08-12
申请号：US11531082
申请日：2006-09-12
申请人： Ken Takeuchi , Takuya Futatsuyama , Koichi Kawai
发明人： Ken Takeuchi , Takuya Futatsuyama , Koichi Kawai
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/105
摘要： A nonvolatile semiconductor memory device includes a memory cell array, read circuit, program circuit, read voltage generating circuit, memory circuit and switching circuit. The read voltage generating circuit generates and supplies a read voltage to the read circuit. The memory circuit stores information which changes the temperature characteristic of a memory cell in the memory cell array. The switching circuit changes the temperature dependency of read voltage generated from the read voltage generating circuit based on information stored in the memory circuit.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，读取电路，程序电路，读取电压产生电路，存储器电路和开关电路。读取电压产生电路产生读取电压并将读取电压提供给读取电路。存储电路存储改变存储单元阵列中的存储单元的温度特性的信息。开关电路基于存储在存储器电路中的信息改变从读取电压产生电路产生的读取电压的温度依赖性。

6. 发明授权

US07286420B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07286420B2
公开(公告)日：2007-10-23
申请号：US11488053
申请日：2006-07-18
申请人： Koichi Kawai
发明人： Koichi Kawai
IPC分类号： G11C29/00
CPC分类号： G11C29/848 , G11C16/04 , G11C29/802 , G11C29/82 , G11C29/835 , G11C2229/723
摘要： A semiconductor memory device including: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of the memory cell array; first data hold circuits configured to hold data for designating whether each column of the memory cell array is defective or not; and a second data hold circuit configured to hold data read out of the first data hold circuits, and to control skipping a defective column address of the memory cell array in accordance with the data read out of the first data hold circuit.
摘要翻译：一种半导体存储器件，包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 读出放大器电路，被配置为读取存储单元阵列的数据; 第一数据保持电路，被配置为保存用于指定存储单元阵列的每列是否有缺陷的数据; 以及第二数据保持电路，被配置为保持从第一数据保持电路读出的数据，并且根据从第一数据保持电路读出的数据来控制跳过存储单元阵列的有缺陷的列地址。

7. 发明授权

US07164605B2 Semiconductor memory device and electric device with the same 有权
标题翻译：半导体存储器件和电器件相同
公开(公告)号：US07164605B2
公开(公告)日：2007-01-16
申请号：US11305193
申请日：2005-12-19
申请人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
发明人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/06
CPC分类号： G11C16/3468
摘要： A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for the first area of the first cell array block and a second area of a second cell array block are simultaneously executed, while the busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of the first area held in the sense amplifier circuits to the chip external, and in a second read cycle selecting the second area in the second cell array block, after the busy signal generation circuit has output a dummy busy signal shorter in time length than the true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of the second area held in the sense amplifier circuits to the chip external.
摘要翻译：半导体存储器件包括：多个单元阵列块，每个单元阵列块中布置有多个存储单元; 用于选择单元阵列块中的存储单元的地址解码电路; 用于读取单元阵列块的单元数据的读出放大器电路; 以及用于向芯片外部产生忙信号的忙信号产生电路，其中在第一读周期中选择第一单元阵列块中的第一区，对第一单元阵列块的第一区进行单元数据读操作，同时执行第二单元阵列块的区域，而忙信号产生电路产生真正的忙信号，然后执行读数据输出操作，以将保持在读出放大器电路中的第一区域的读出数据输出到芯片外部，并且在第二读取周期中选择第二单元阵列块中的第二区域，在忙信号产生电路在不执行单元数据读取操作的情况下输出比真实忙信号更短的时间长度的虚拟忙信号，读取执行数据输出操作，以将保持在读出放大器电路中的第二区域的读出数据输出到芯片外部。

8. 发明授权

US07082054B2 Semiconductor storage device having page copying function 有权
公开(公告)号：US07082054B2
公开(公告)日：2006-07-25
申请号：US11219193
申请日：2005-09-02
申请人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C16/04
CPC分类号： G11C16/105 , G11C7/1006 , G11C7/1021 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/3431 , H01L27/115
摘要： Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to the column address. The latch circuit specified in accordance with the column address is supplied with the data to be rewritten. The latch circuit specified in accordance with its address latches the data to be rewritten, whereby rewriting of the data is performed. The data of one page after rewritten is written into the page in the memory cell array that corresponds to the page address of a copy destination.

9. 发明授权

US07023741B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US07023741B2
公开(公告)日：2006-04-04
申请号：US10318167
申请日：2002-12-13
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/00
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

10. 发明申请

US20060002213A1 Semiconductor storage device having page copying function 有权
公开(公告)号：US20060002213A1
公开(公告)日：2006-01-05
申请号：US11219193
申请日：2005-09-02
申请人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C7/00
CPC分类号： G11C16/105 , G11C7/1006 , G11C7/1021 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/3431 , H01L27/115
摘要： Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to the column address. The latch circuit specified in accordance with the column address is supplied with the data to be rewritten. The latch circuit specified in accordance with its address latches the data to be rewritten, whereby rewriting of the data is performed. The data of one page after rewritten is written into the page in the memory cell array that corresponds to the page address of a copy destination.

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