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1. 发明申请

US20120325746A1 POLYMER MEMBRANE FOR WATER TREATMENT AND METHOD FOR MANUFACTURE OF SAME, AND WATER TREATMENT METHOD 审中-公开
标题翻译：水处理用聚合物膜及其制造方法及水处理方法
公开(公告)号：US20120325746A1
公开(公告)日：2012-12-27
申请号：US13582528
申请日：2011-03-02
申请人： Toshihiro Tamai , Naotaka Oyabu , Saki Tanimura , Takashi Osugi , Ryuichi Matsuo
发明人： Toshihiro Tamai , Naotaka Oyabu , Saki Tanimura , Takashi Osugi , Ryuichi Matsuo
IPC分类号： B01D67/00 , C08F114/06 , B26D3/00 , C02F1/00 , B01D69/08
CPC分类号： B01D69/087 , B01D61/145 , B01D67/0016 , B01D69/02 , B01D69/08 , B01D71/30 , B01D2325/04 , B01D2325/24 , B29C48/0022 , B29L2031/755 , C02F1/444 , C02F3/1268 , C02F3/1273 , Y02W10/15 , Y10T29/49
摘要： A polymer membrane for water treatment, characterized in comprising a hollow fiber membrane having a self-supporting design composed of the substantially single principal structural material, with an outer diameter of 3.6 mm to 10 mm and a ratio of outer diameter to thickness, SDR, of 3.6 to 34.
摘要翻译：一种用于水处理的聚合物膜，其特征在于包括具有由基本上单一的主要结构材料构成的自支撑设计的中空纤维膜，外径为3.6mm至10mm，外径与厚度之比SDR，为3.6至34。

2. 发明授权

US08181795B2 Polymer membrane for water treatment 有权
标题翻译：聚合物膜用于水处理
公开(公告)号：US08181795B2
公开(公告)日：2012-05-22
申请号：US13382204
申请日：2010-07-05
申请人： Toshihiro Tamai , Saki Tanimura , Naotaka Oyabu , Ryuichi Matsuo , Takashi Osugi , Yuki Goto , Tadashi Okamoto
发明人： Toshihiro Tamai , Saki Tanimura , Naotaka Oyabu , Ryuichi Matsuo , Takashi Osugi , Yuki Goto , Tadashi Okamoto
IPC分类号： B01D63/02 , B01D71/30 , B01D63/00
CPC分类号： B01D71/30 , B01D61/145 , B01D2323/12 , B01D2325/34 , C02F1/444
摘要： A polymer membrane for water treatment contained a chlorinated vinyl chloride resin with a chlorine content of 58 to 73.2%. According to the present invention, it is possible to provide polymer membranes for water treatment that, along with being able to achieve sufficient filtration capacity and water permeability, have extremely high strength.
摘要翻译：用于水处理的聚合物膜含有氯含量为58-73.2％的氯化氯乙烯树脂。根据本发明，可以提供水处理用聚合物膜，其能够实现充分的过滤能力和透水性，具有极高的强度。

3. 发明申请

US20120097605A1 POLYMER MEMBRANE FOR WATER TREATMENT 有权
标题翻译：聚合物水处理膜
公开(公告)号：US20120097605A1
公开(公告)日：2012-04-26
申请号：US13382204
申请日：2010-07-05
申请人： Toshihiro Tamai , Saki Tanimura , Naotaka Oyabu , Ryuichi Matsuo , Takashi Osugi , Yuki Goto , Tadashi Okamoto
发明人： Toshihiro Tamai , Saki Tanimura , Naotaka Oyabu , Ryuichi Matsuo , Takashi Osugi , Yuki Goto , Tadashi Okamoto
IPC分类号： B01D71/28 , C02F1/00
CPC分类号： B01D71/30 , B01D61/145 , B01D2323/12 , B01D2325/34 , C02F1/444
摘要： A polymer membrane for water treatment contained a chlorinated vinyl chloride resin with a chlorine content of 58 to 73.2%. According to the present invention, it is possible to provide polymer membranes for water treatment that, along with being able to achieve sufficient filtration capacity and water permeability, have extremely high strength.
摘要翻译：用于水处理的聚合物膜含有氯含量为58-73.2％的氯化氯乙烯树脂。根据本发明，可以提供水处理用聚合物膜，其能够实现充分的过滤能力和透水性，具有极高的强度。

4. 发明授权

US09193815B2 Polymer membrane for water treatment and method for manufacture of same 有权
标题翻译：水处理用聚合物膜及其制造方法
公开(公告)号：US09193815B2
公开(公告)日：2015-11-24
申请号：US13582534
申请日：2011-03-02
申请人： Toshihiro Tamai , Yuki Goto , Takashi Osugi , Ryuichi Matsuo , Naotaka Oyabu
发明人： Toshihiro Tamai , Yuki Goto , Takashi Osugi , Ryuichi Matsuo , Naotaka Oyabu
IPC分类号： B01D63/00 , B01D39/00 , B01D39/14 , B01D71/28 , C08F214/06 , B01D67/00 , B01D69/08 , B01D71/76 , C08F214/08 , B01D71/30 , B01D71/38 , C08F226/10 , C08F220/28 , C08F220/20
CPC分类号： C08F214/06 , B01D67/0093 , B01D69/08 , B01D71/30 , B01D71/38 , B01D71/76 , B01D2325/36 , C08F8/12 , C08F214/08 , C08F220/20 , C08F226/10 , C08F2220/286 , C08F2810/50 , C08F2220/281 , C08F218/08
摘要： A polymer membrane for water treatment composed of a vinyl chloride copolymer comprising a vinyl chloride monomer and a hydrophilic monomer.
摘要翻译：一种用于水处理的聚合物膜，由包含氯乙烯单体和亲水单体的氯乙烯共聚物组成。

5. 发明申请

US20120318730A1 POLYMER MEMBRANE FOR WATER TREATMENT AND METHOD FOR MANUFACTURE OF SAME 有权
标题翻译：用于水处理的聚合物膜及其制造方法
公开(公告)号：US20120318730A1
公开(公告)日：2012-12-20
申请号：US13582534
申请日：2011-03-02
申请人： Toshihiro Tamai , Yuki Goto , Takashi Osugi , Ryuichi Matsuo , Naotaka Oyabu
发明人： Toshihiro Tamai , Yuki Goto , Takashi Osugi , Ryuichi Matsuo , Naotaka Oyabu
IPC分类号： B01D71/64 , B01D71/56 , B01D63/02 , B01D71/38
CPC分类号： C08F214/06 , B01D67/0093 , B01D69/08 , B01D71/30 , B01D71/38 , B01D71/76 , B01D2325/36 , C08F8/12 , C08F214/08 , C08F220/20 , C08F226/10 , C08F2220/286 , C08F2810/50 , C08F2220/281 , C08F218/08
摘要： A polymer membrane for water treatment composed of a vinyl chloride copolymer comprising a vinyl chloride monomer and a hydrophilic monomer.
摘要翻译：一种用于水处理的聚合物膜，由包含氯乙烯单体和亲水单体的氯乙烯共聚物组成。

6. 发明授权

US5781468A Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same 失效
标题翻译：半导体存储器件包括以不同访问速度操作的两种存储器单元及其操作和制造方法
公开(公告)号：US5781468A
公开(公告)日：1998-07-14
申请号：US851757
申请日：1997-05-06
申请人： Ryuichi Matsuo , Tomohisa Wada , Kazutoshi Hirayama , Shigeki Ohbayashi
发明人： Ryuichi Matsuo , Tomohisa Wada , Kazutoshi Hirayama , Shigeki Ohbayashi
IPC分类号： G11C11/41 , G11C11/00 , G11C11/401 , H01L27/10 , H01L27/105 , G11C11/24
CPC分类号： H01L27/105 , G11C11/005
摘要： A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.
摘要翻译：半导体存储器件包括动态存储单元阵列，静态存储单元阵列，多个字线，多个DRAM位线对和多个SRAM位线对。动态存储单元阵列包括以矩阵形状排列的多个动态存储单元。静态存储单元阵列被布置成与动态存储单元阵列相邻。静态存储单元阵列包括以矩阵形状排列的静态存储单元。多个字线被布置成多行。每个字线连接到布置在相应行中的动态和静态存储单元。多个DRAM位线对排列成多列。每个DRAM位线对连接到动态存储单元。在其他多个列中布置有多个SRAM位线对。每个SRAM位线对连接到布置在相应列中的静态存储单元。

7. 发明授权

US5726950A Synchronous semiconductor memory device performing input/output of data in a cycle shorter than an external clock signal cycle 失效
标题翻译：同步半导体存储器件以比外部时钟信号周期短的周期执行数据的输入/输出
公开(公告)号：US5726950A
公开(公告)日：1998-03-10
申请号：US779829
申请日：1997-01-07
申请人： Yasuyuki Okamoto , Ryuichi Matsuo
发明人： Yasuyuki Okamoto , Ryuichi Matsuo
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C29/00 , G11C29/48 , G11C8/00
CPC分类号： G11C7/1093 , G11C29/48 , G11C7/1051 , G11C7/1072 , G11C7/1078
摘要： An input circuit 200 includes first to fourth switching transistors T1-T4 to be controlled by clock signals CLK and /CLK, and two latch circuits 202 and 204. In response to a rising edge of the clock signal, switching transistor T1 is turned on, and latch circuit 202 takes in data. In response to a falling edge of clock signal CLK, switching transistor T3 is turned on, and latch circuit 204 takes in the data. Since input and output of the data are performed at both the rising edge and the falling edge of the clock signal, the operation can be performed at double the frequency.
摘要翻译：输入电路200包括由时钟信号CLK和/ CLK控制的第一至第四开关晶体管T1-T4以及两个锁存电路202和204.响应于时钟信号的上升沿，开关晶体管T1导通，并且锁存电路202接收数据。响应于时钟信号CLK的下降沿，开关晶体管T3导通，锁存电路204接收数据。由于在时钟信号的上升沿和下降沿均执行数据的输入和输出，所以可以以两倍的频率进行操作。

8. 发明授权

US5646885A Fast accessible non-volatile semiconductor memory device 失效
标题翻译：快速访问的非易失性半导体存储器件
公开(公告)号：US5646885A
公开(公告)日：1997-07-08
申请号：US395249
申请日：1995-02-27
申请人： Ryuichi Matsuo , Makoto Yamamoto
发明人： Ryuichi Matsuo , Makoto Yamamoto
IPC分类号： G11C17/00 , G11C11/412 , G11C14/00 , G11C16/04 , G11C11/24
CPC分类号： G11C11/412 , G11C14/00 , G11C16/0441
摘要： A non-volatile SRAM cell (MC) includes floating gate type transistors (1a, 1b) arranged between power supply nodes (4a, 4b) and storage nodes (A, B), and flip-flops (2a, 2b) holding signal potentials of the storage nodes. The floating gate type transistor has a drain connected to the power supply node, and a control gate connected to a control electrode node (5). Voltages are applied independently to the drains and the control gate of the floating gate type transistor, whereby a large amount of hot electrons are efficiently generated by avalanche breakdown and are accelerated to be injected into the floating gate. Removal of electrons is achieved by the voltages applied to the control gate and the drain. In the non-volatile SRAM cell utilizing the floating gate type transistor, injection and removal of electrons with respect to the floating gate are efficiently performed to change a threshold voltage for reliably storing information in a non-volatile manner.
摘要翻译：非易失性SRAM单元（MC）包括布置在电源节点（4a，4b）和存储节点（A，B）之间的浮动栅型晶体管（1a，1b）和保持信号电位的触发器（2a，2b）的存储节点。浮栅型晶体管具有连接到电源节点的漏极和连接到控制电极节点（5）的控制栅极。电压独立地施加到浮栅型晶体管的漏极和控制栅极，由此通过雪崩击穿有效地产生大量的热电子，并被加速以注入浮栅。通过施加到控制栅极和漏极的电压来实现电子的去除。在利用浮栅型晶体管的非易失性SRAM单元中，有效地执行相对于浮置栅极的电子注入和去除，以便以非易失性方式可靠地存储信息来改变阈值电压。

9. 发明授权

US08617445B2 Process for producing oriented thermoplastic polyester resin sheet, and laminate-molded body 有权
标题翻译：制造取向热塑性聚酯树脂片和层压成型体的方法
公开(公告)号：US08617445B2
公开(公告)日：2013-12-31
申请号：US11886235
申请日：2006-02-17
申请人： Shigeru Ogasawara , Hirotsugu Yoshida , Hisashi Eguchi , Ryuichi Matsuo
发明人： Shigeru Ogasawara , Hirotsugu Yoshida , Hisashi Eguchi , Ryuichi Matsuo
IPC分类号： B28B11/08
CPC分类号： B32B27/36 , B29C55/04 , B29C65/086 , B29C65/4815 , B29C65/483 , B29C66/1122 , B29C66/21 , B29C66/344 , B29C66/45 , B29C66/71 , B29C66/7315 , B29C66/73711 , B29C66/73774 , B29C66/7392 , B29C66/73921 , B29C66/81433 , B29C66/83411 , B29C66/83413 , B29K2067/00 , B29K2067/043 , B29K2067/046 , B29K2101/12 , B29K2105/0845 , B29K2105/0854 , B29K2995/005 , B29K2995/0089 , B29L2009/00 , B32B37/1207 , B32B2037/1215 , B32B2307/514 , B32B2310/028 , B32B2367/00 , Y10T428/2817 , Y10T428/2848 , Y10T428/31786 , Y10T442/3854 , Y10T442/674 , B29K2067/003 , B29K2067/006
摘要： The present invention provides a process for producing an oriented thermoplastic polyester resin sheet which is excellent in tensile strength, tencile modulas and heat resistance, and a light laminate-molded body using the same, which has a low linear expansion coefficient and is excellent in impact resistance, durability, easiness of handling, productivity, and others. A process for producing an oriented thermoplastic polyester resin sheet, which includes: pultrusion-drawing a thermoplastic polyester resin sheet in an amorphous state at a temperature from the glass transition temperature of the thermoplastic polyester resin −20° C. to the glass transition temperature of the thermoplastic polyester resin +20° C.; and then drawing the resultant uniaxially at a temperature higher than the temperature for the pultrusion-drawing. A laminate-molded body, wherein a thermoplastic resin layer is laminated on each of the surfaces of the resultant oriented thermoplastic polyester resin sheet.
摘要翻译：本发明提供一种制造拉伸强度，十倍体阻力和耐热性优异的取向热塑性聚酯树脂片材的方法，使用该方法具有低线膨胀系数和冲击性优异的轻层压体电阻，耐用性，易于处理，生产率等。一种取向热塑性聚酯树脂片的制造方法，其特征在于，包括：在从所述热塑性聚酯树脂的玻璃化转变温度-20℃至-20℃的温度下，以非晶态拉伸拉伸热塑性聚酯树脂片，热塑性聚酯树脂+ 20°C。然后在高于拉拔拉拔温度的温度下单轴拉伸。层压成型体，其中在所得到的取向热塑性聚酯树脂片的每个表面上层压热塑性树脂层。

10. 发明授权

US5659515A Semiconductor memory device capable of refresh operation in burst mode 失效
标题翻译：能够以突发模式刷新操作的半导体存储器件
公开(公告)号：US5659515A
公开(公告)日：1997-08-19
申请号：US520190
申请日：1995-08-28
申请人： Ryuichi Matsuo , Tomohisa Wada
发明人： Ryuichi Matsuo , Tomohisa Wada
IPC分类号： G11C7/10 , G11C11/401 , G11C11/405 , G11C11/406 , G11C7/00
CPC分类号： G11C7/103 , G11C11/406
摘要： A semiconductor memory device comprising a memory cell array, a row decoder, an input/output register train, a burst counter, an input/output bus, a refresh counter and a multiplexer. The memory cell array includes a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells. The input/output register train has a plurality of registers corresponding to the bit line pairs. Each of the registers is connected to the corresponding bit line pair. The input/output bus inputs and outputs data to and from the register train in response to a signal from the burst counter. The multiplexer supplies the row decoder with an external address signal as an internal address signal. After data is transferred from any bit line pair to the register or before data is transferred from any register to the bit line pair, the multiplexer supplies the row decoder with a refresh address signal from the refresh counter in place of the external address signal. This allows a refresh operation to take place during a burst read/write operation of data.
摘要翻译：包括存储单元阵列，行解码器，输入/输出寄存器列，突发计数器，输入/输出总线，刷新计数器和多路复用器的半导体存储器件。存储单元阵列包括多个字线，多个位线对和多个存储单元。输入/输出寄存器列具有对应于位线对的多个寄存器。每个寄存器都连接到相应的位线对。输入/输出总线响应于来自脉冲串计数器的信号，输入和输出数据到和从寄存器串中输出数据。多路复用器为行解码器提供外部地址信号作为内部地址信号。在数据从任何位线对传输到寄存器之后，或者在数据从任何寄存器传送到位线对之前，多路复用器为行解码器提供来自刷新计数器的刷新地址信号来代替外部地址信号。这允许在数据的突发读/写操作期间进行刷新操作。

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