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1. 发明授权

US5969966A Power converting apparatus and method using a multiple three-phase PWM cycloconverter system 失效
标题翻译：使用多重三相PWM循环变频器系统的电力转换装置和方法
公开(公告)号：US5969966A
公开(公告)日：1999-10-19
申请号：US29262
申请日：1998-03-09
申请人： Toshihiro Sawa , Tsuneo Kume , Koichi Hirano
发明人： Toshihiro Sawa , Tsuneo Kume , Koichi Hirano
IPC分类号： H02M5/27 , H02P27/16 , H02M13/02 , H02M5/257 , H02M5/275
CPC分类号： H02P27/16 , H02M5/271 , H02M7/487 , Y02P80/116
摘要： A power converting apparatus and a power converting method for driving a high voltage AC motor at a variable speed. Conventional invertor systems cannot solve technical subjects such as energy conservation, resource conservation, miniaturization, efficiency promotion and voltage and current waveform distortion suppression for improvement in environment needed by the market, and cannot solve another technical subject of improvement in redundancy such that, upon failure, operation is performed with a normal part. In the present invention, a power converting apparatus of a multiple three-phase pulse width modulation cycloconverter system for driving a high voltage AC motor at a variable speed is used, and bidirectional semiconductor switches are controlled so that voltages of AC outputs to be outputted to single-phase AC terminals of three-phase/single-phase pulse width modulation cycloconverters may have a same phase in each of units but electric angles of basic wave voltage phases may be different by 120 degrees from each other among the three units to drive a high voltage AC motor. If one of the cycloconverters fails, then the single-phase AC terminals of the failed cycloconverter are short-circuited and three sets of switches each consisting of two bidirectional semiconductor switches connected to three-phase AC terminals of the cycloconverters of the other two units in the same group as the failed cycloconverter are successively rendered conducting one by one set at equal time intervals to short-circuit the three sets of the bidirectional semiconductor switches to drive the high voltage AC motor at a variable speed.
摘要翻译： PCT No.PCT / JP96 / 02495 371日期1998年3月9日 102（e）1998年3月9日PCT PCT 1996年9月4日PCT公布。公开号WO97 / 09773 日期1997年3月13日电变换装置和用于以可变速度驱动高压AC电动机的电力转换方法。传统的逆变器系统不能解决诸如节能，资源节约，小型化，提高效率以及电压和电流波形失真抑制等技术课题，以改善市场所需的环境，并且不能解决另一个冗余性提高的技术课题，使得在故障时，用正常部分进行操作。在本发明中，使用用于以可变速度驱动高压AC电动机的多重三相脉宽调制循环变频器系统的电力转换装置，并且控制双向半导体开关，使得输出的AC输出的电压被输出到三相/单相脉宽调制循环变换器的单相交流端子可以在每个单元中具有相同的相位，但是三个单元中的基波电压相位的电角度可以彼此相差120度以驱动高压交流电机。如果其中一个循环变频器发生故障，则故障循环变频器的单相交流端子短路，每组由两个双向半导体开关组成的三组开关连接到其他两个单元的循环变频器的三相交流端子与故障循环换流器相同的组以相等的时间间隔逐个连续地进行导通，以使三组双向半导体开关短路，以可变速度驱动高压AC电动机。

2. 发明授权

US08617943B2 Method for making a semiconductor device on a flexible substrate 有权
标题翻译：在柔性基板上制造半导体器件的方法
公开(公告)号：US08617943B2
公开(公告)日：2013-12-31
申请号：US12746440
申请日：2009-07-22
申请人： Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano , Yoshihisa Yamashita , Shingo Komatsu
发明人： Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano , Yoshihisa Yamashita , Shingo Komatsu
IPC分类号： H01L21/00
CPC分类号： H01L29/78603 , H01L24/19 , H01L24/82 , H01L27/1218 , H01L29/66765 , H01L29/78609 , H01L29/78681 , H01L29/7869 , H01L51/0024 , H01L51/003 , H01L51/0097 , H01L51/0541 , H01L51/0545 , H01L2221/68377 , H01L2224/04105 , H01L2224/73267 , H01L2224/76155 , H01L2224/82039 , H01L2224/82102 , H01L2224/92144 , H01L2224/92244 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01047 , H01L2924/01049 , H01L2924/01056 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01078 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/10329 , H01L2924/12042 , H01L2924/15788 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.
摘要翻译：一种制造柔性半导体器件的方法包括：制备包括依次形成的第一金属层10，无机绝缘层20，半导体层30和第二金属层40的层状膜80; 蚀刻第一金属层10以形成栅电极12g; 将树脂层50压接到设置有栅电极12g的层叠膜80的表面，以使栅电极12g嵌入树脂层50中; 并且蚀刻第二金属层40以形成源电极42s和漏电极42d，其中栅电极12g上的无机绝缘层20用作栅极绝缘膜22，并且源电极42s和漏极之间的半导体层30 无机绝缘层20上的电极42d用作通道32。

3. 发明授权

US08525178B2 Flexible semiconductor device and method for producing the same 有权
标题翻译：柔性半导体器件及其制造方法
公开(公告)号：US08525178B2
公开(公告)日：2013-09-03
申请号：US13498700
申请日：2011-04-14
申请人： Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
发明人： Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
IPC分类号： H01L29/04
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/124 , H01L27/1262 , H01L27/1292 , H01L27/3244 , H01L29/78603 , H01L2251/5338
摘要： A flexible semiconductor device includes an insulating film on which a semiconductor element is formed. The top and bottom surfaces of the insulating film have a top wiring pattern layer and a bottom wiring pattern layer, respectively. The semiconductor element includes a semiconductor layer formed on the top surface of the insulating film, a source electrode and a drain electrode formed on the top surface of the insulating film so as to contact the semiconductor layer, and a gate electrode formed on the bottom surface of the insulating film so as to be opposite the semiconductor layer. A first thickness, which is the thickness of the insulating film facing the source electrode, the drain electrode, the top wiring pattern layer, and the bottom wiring pattern layer, is greater than a second thickness, which is the thickness of the insulating film between the gate electrode and the semiconductor layer.
摘要翻译：柔性半导体器件包括其上形成有半导体元件的绝缘膜。绝缘膜的顶表面和底表面分别具有顶部布线图案层和底部布线图案层。半导体元件包括形成在绝缘膜的顶表面上的半导体层，形成在绝缘膜的顶表面上以与半导体层接触的源电极和漏电极，以及形成在底表面上的栅电极的绝缘膜与半导体层相对。作为与源极电极，漏极电极，顶部布线图案层和底部布线图案层相对的绝缘膜的厚度的第一厚度大于第二厚度，其是第二厚度，其是绝缘膜的厚度栅电极和半导体层。

4. 发明申请

US20130032797A1 FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20130032797A1
公开(公告)日：2013-02-07
申请号：US13641793
申请日：2011-12-19
申请人： Koichi Hirano , Shingo Komatsu , Yasuteru Saito , Naoki Ike
发明人： Koichi Hirano , Shingo Komatsu , Yasuteru Saito , Naoki Ike
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/7869 , H01L29/66742 , H01L29/66969 , H01L29/78693
摘要： The present invention achieves a formation of a metal oxide film of a thin film transistor with a simplified process. The present invention is concerned with a method for manufacturing a field-effect transistor comprising a gate electrode, a source electrode, a drain electrode, a channel layer and a gate insulating layer wherein the channel layer is formed by using a metal salt-containing composition comprising a metal salt, a polyvalent carboxylic acid having a cis-form structure of —C(COOH)═C(COOH)—, an organic solvent and a water wherein a molar ratio of the polyvalent carboxylic acid to the metal salt is in the range of 0.5 to 4.0.
摘要翻译：本发明通过简化的工艺实现了薄膜晶体管的金属氧化物膜的形成。本发明涉及一种制造场效应晶体管的方法，该场效应晶体管包括栅电极，源电极，漏电极，沟道层和栅极绝缘层，其中通过使用含金属盐的组合物形成沟道层包括金属盐，具有-C（COOH）= C（COOH） - 的顺式结构的多元羧酸，有机溶剂和水，其中多价羧酸与金属盐的摩尔比为范围为0.5至4.0。

5. 发明授权

US07910403B2 Metal particles-dispersed composition and flip chip mounting process and bump-forming process using the same 有权
标题翻译：金属颗粒分散组合物和倒装芯片安装工艺以及使用其的凸块形成工艺
公开(公告)号：US07910403B2
公开(公告)日：2011-03-22
申请号：US11885562
申请日：2006-03-06
申请人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita
发明人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita
IPC分类号： H01L21/00
CPC分类号： H01L24/81 , H01L21/6835 , H01L23/49883 , H01L24/11 , H01L24/12 , H01L24/16 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/11005 , H01L2224/1141 , H01L2224/1152 , H01L2224/11524 , H01L2224/13099 , H01L2224/16 , H01L2224/293 , H01L2224/294 , H01L2224/73104 , H01L2224/83886 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H05K3/323 , H05K3/3484 , H05K2201/10977 , H05K2203/0425 , H05K2203/087 , H05K2203/1178 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A flip chip mounting process wherein a semiconductor chip and a circuit substrate are electrically interconnected. The process includes the steps of preparing a semiconductor chip on which a first plurality of electrodes are formed and a circuit substrate on which a second plurality of electrodes are formed; supplying a composition onto a surface of the circuit substrate, such surface being provided with second plurality of electrodes; bringing the semiconductor chip into contact with a surface of said composition such that the first plurality of electrodes are opposed to the second plurality of electrodes; and heating the circuit substrate, and thereby electrical connections including a metal component constituting the metal particles dispersed in the composition are formed between the first plurality of electrodes and the second plurality of electrodes. Also, a thermoset resin layer is formed between the semiconductor chip and the circuit substrate.
摘要翻译：一种倒装芯片安装工艺，其中半导体芯片和电路基板电连接。该方法包括制备其上形成有第一多个电极的半导体芯片和形成有第二多个电极的电路基板的步骤; 在电路基板的表面上提供组合物，该表面设置有第二多个电极; 使所述半导体芯片与所述组合物的表面接触，使得所述第一多个电极与所述第二多个电极相对; 并且加热电路基板，从而在第一多个电极和第二多个电极之间形成包括构成分散在组合物中的金属颗粒的金属组分的电连接。此外，在半导体芯片和电路基板之间形成热固性树脂层。

6. 发明申请

US20110042677A1 FLEXIBLE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：柔性半导体器件及其制造方法
公开(公告)号：US20110042677A1
公开(公告)日：2011-02-24
申请号：US12863202
申请日：2009-11-13
申请人： Takeshi Suzuki , Kenichi Hotehama , Koichi Hirano , Seiichi Nakatani
发明人： Takeshi Suzuki , Kenichi Hotehama , Koichi Hirano , Seiichi Nakatani
IPC分类号： H01L33/08 , H01L21/336
CPC分类号： H01L29/66742 , H01L29/66765 , H01L29/786 , H01L29/78603 , H01L29/78681 , H01L29/7869
摘要： There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprises a metal layer comprising a gate electrode, a source electrode and a drain electrode; a metal oxide film made from a metal which constitutes the metal layer and formed over a surface region of the metal layer; and a semiconductor layer formed above the gate electrode via the metal oxide film. In the flexible semiconductor device, uncovered portions, each of which is not covered with the metal oxide film, are locally formed in the surface region of the metal layer; and also electrical connections are formed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer via the uncovered portions.
摘要翻译：提供了一种柔性半导体器件。本发明的柔性半导体器件包括由栅电极，源电极和漏电极组成的金属层; 由金属制成的金属氧化物膜，其构成金属层并形成在金属层的表面区域上; 以及通过金属氧化物膜形成在栅极电极上方的半导体层。在柔性半导体器件中，在金属层的表面区域局部形成未被金属氧化物膜覆盖的未覆盖部分，并且还通过未覆盖部分在源电极和半导体层之间以及在漏电极和半导体层之间形成电连接。

7. 发明申请

US20100261321A1 METHOD FOR MANUFACTURING FLEXIBLE SEMICONDUCTOR DEVICE 有权
标题翻译：制造柔性半导体器件的方法
公开(公告)号：US20100261321A1
公开(公告)日：2010-10-14
申请号：US12681399
申请日：2009-07-30
申请人： Koichi Hirano , Seiichi Nakatani , Tatsuo Ogawa
发明人： Koichi Hirano , Seiichi Nakatani , Tatsuo Ogawa
IPC分类号： H01L21/336
CPC分类号： H01L51/0541 , H01L51/0004 , H01L51/0022 , H01L51/0097 , H01L51/107 , Y02E10/549 , Y02P70/521
摘要： There is provided a method for manufacturing a flexible semiconductor device. The manufacturing method is characterized by comprising (i) a step of forming an insulating film on the upper surface of a resin film, (ii) a step of forming a pattern of extraction electrodes on the upper surface of the resin film, (iii) a step of forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the pattern of extraction electrodes, and (iv) a step of forming a sealing resin layer on the upper surface of the resin film in such a manner that the sealing resin layer covers the semiconductor layer and the pattern of extraction electrodes, wherein at least one forming step among the above (i) to (iv) is carried out by a printing method. In the manufacturing method, various layers can be formed by a simple printing process without using a vacuum process, photolithography, or the like.
摘要翻译：提供了一种用于制造柔性半导体器件的方法。（i）在树脂膜的上表面形成绝缘膜的工序，（ii）在树脂膜的上表面形成引出电极的图案的工序，（iii）以使得半导体层与引出电极的图案接触的方式在绝缘膜上形成半导体层的步骤，以及（iv）在树脂膜的上表面上形成密封树脂层的步骤密封树脂层覆盖半导体层和提取电极的图案的方式，其中上述（i）至（iv）中的至少一个形成步骤通过印刷方法进行。在制造方法中，可以通过简单的印刷工艺形成各种层，而不使用真空工艺，光刻等。

8. 发明授权

US07748110B2 Method for producing connection member 有权
标题翻译：连接部件的制造方法
公开(公告)号：US07748110B2
公开(公告)日：2010-07-06
申请号：US11826758
申请日：2007-07-18
申请人： Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
发明人： Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
IPC分类号： H05K3/36
CPC分类号： H05K3/403 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H01R13/2414 , H05K1/0218 , H05K1/0284 , H05K1/141 , H05K1/145 , H05K1/182 , H05K3/20 , H05K3/3442 , H05K3/361 , H05K3/366 , H05K3/368 , H05K2201/043 , H05K2201/048 , H05K2201/049 , H05K2201/055 , H05K2201/056 , H05K2201/09036 , H05K2201/10515 , H05K2201/10689 , H05K2203/302 , Y10T29/49117 , Y10T29/49126 , Y10T29/49208 , H01L2924/00
摘要： A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.
摘要翻译：可以在没有通孔形成步骤的情况下制造连接构件。连接构件包括绝缘基板，其具有上表面，与上表面相对的下表面和连接这些表面的侧表面; 以及至少一个通过侧面从上表面延伸到下表面的布线。

9. 发明申请

US20070243664A1 Flip-Chip Mounting Method and Bump Formation Method 有权
标题翻译：倒装芯片安装方法和凸块形成方法
公开(公告)号：US20070243664A1
公开(公告)日：2007-10-18
申请号：US11579299
申请日：2006-03-07
申请人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita , Seiichi Nakatani
发明人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita , Seiichi Nakatani
IPC分类号： H05K3/34 , H01L21/00 , H01L21/44 , H05K3/00
CPC分类号： H01L21/563 , B23K35/0244 , H01L21/67144 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/75 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1131 , H01L2224/13099 , H01L2224/1319 , H01L2224/133 , H01L2224/16 , H01L2224/75 , H01L2224/83192 , H01L2224/8321 , H01L2224/83815 , H01L2224/83886 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/18161 , H01L2924/30105 , H05K3/323 , H05K3/3436 , H05K3/3484 , H05K2201/10977 , H05K2203/1361 , Y02P70/613 , Y10T29/53178 , H01L2224/05599
摘要： [Problem] To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability. [Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals. Thereafter, the semiconductor chip 20 and the circuit board 21 are taken out of the dipping bath 40, and the melted resin 14 having permeated into the gap between the semiconductor chip 20 and the circuit board 21 is cured, so as to complete a flip-chip mounting body.
摘要翻译： [问题]提供一种适用于下一代LSI的倒装安装并具有高生产率和高可靠性的倒装芯片安装方法和凸块形成方法。解决问题的手段具有多个电极端子12的半导体芯片20被保持为具有多个连接端子11的电路板21，其间设置有给定的间隙，并且半导体芯片20和电路板21 将该状态浸渍在包含熔融的焊料颗粒的熔融树脂14的浸渍浴40中一段给定的时间。在该浸渍过程中，熔融的焊料颗粒自组装在电路板21的连接端子11和半导体芯片20的电极端子12之间，从而在这些端子之间形成连接器22。此后，半导体芯片20和电路板21从浸渍浴40中取出，并且已经渗透到半导体芯片20和电路板21之间的间隙中的熔融树脂14固化，芯片安装体。

10. 发明申请

US20070183837A1 Ball-point pen 失效
标题翻译：圆珠笔
公开(公告)号：US20070183837A1
公开(公告)日：2007-08-09
申请号：US10589973
申请日：2005-02-16
申请人： Koichi Hirano
发明人： Koichi Hirano
IPC分类号： B43K7/00 , B43K7/10
CPC分类号： B43K1/08 , B43K7/00 , B43K7/10
摘要： A ball-point pen, wherein a cover member (6) is fitted to a joint member (3) connecting a writing tip (1) rotatably supporting a writing ball (2) at the tip thereof to an ink storage tube. When the cover member (6) is fitted to the joint member (3) along the outer peripheral surface thereof, a part of the cover member does not come within 0.2 mm (within the range of the chain double-dashed line) from around the writing tip. Thus, even if the accuracies of parts and assembly machines are dispersed, a problem with an existing ball-point pen wherein a cover member is brought into contact with a writing tip and the writing tip is damaged in an assembly step can be avoided.
摘要翻译：一种圆珠笔，其中盖构件（6）装配到将可旋转地支撑着书写球（2）的书写笔尖（1）的前端连接到墨水储存管的接合构件（3）上。当盖构件（6）沿着其外周面装配到接头构件（3）时，盖构件的一部分不会从其周围的0.2mm（在双点划线的范围内）写作技巧因此，即使部件和组装机的精度分散，也可以避免在组装步骤中使盖部件与书写尖端接触并且笔尖被损坏的现有圆珠笔的问题。

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