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    • 1. 发明授权
    • Apparatus for correcting vertical contours
    • 用于校正垂直轮廓的装置
    • US06424383B1
    • 2002-07-23
    • US09284876
    • 1999-04-22
    • Katsumi TeraiNaoji OkumuraYutaka NioKazuhito Tanaka
    • Katsumi TeraiNaoji OkumuraYutaka NioKazuhito Tanaka
    • H04N521
    • H04N5/208
    • An object is to provide a vertical contour correcting device for a video signal which reduces noise without deteriorating effect of the entire contour correction. A vertical contour correcting device (VCP1) which corrects vertical contour components (S1v, S1v′) of a video signal (S1) with a given quantity of correction (K) to enhance the vertical contour (Ev) of the video signal (S1) comprises a vertical contour component extracting device (3) for detecting said vertical contour components (S1v, S1v′) from said video signal (S1), a vertical contour component correlation detector (3, 29, 8c, 8d, 4) for detecting correlation between horizontally adjacent vertical contour components (Sb, Sb′, Sb′′) from said detected vertical contour components (S1v, S1v′), and a controller (5) for determining said quantity of correction (K) on the basis of said detected correlation (Sj1), thereby varying the quantity of correction (K) in accordance with the correlation (Sj1).
    • 一种垂直轮廓校正装置(VCP1),用于校正视频信号的垂直轮廓分量(S1v,S1v')(垂直轮廓校正装置) S1)具有用于增强视频信号(S1)的垂直轮廓(Ev)的给定量的校正(K)包括垂直轮廓分量提取装置(3),用于从所述垂直轮廓分量(S1v,S1v')检测所述垂直轮廓分量 视频信号(S1),用于检测来自所检测的垂直轮廓分量(S1v)的水平相邻垂直轮廓分量(Sb,Sb',Sb“)之间的相关性的垂直轮廓分量相关检测器(3,29,8c,8d,4) ,S1v'),以及控制器(5),用于根据所述检测到的相关(Sj1)确定所述校正量(K),从而根据相关(Sj1)改变校正量(K)。
    • 2. 发明授权
    • Block noise detector and block noise eliminator
    • 块噪声检测器和阻塞噪声消除器
    • US06738528B1
    • 2004-05-18
    • US09463215
    • 2000-01-21
    • Yutaka NioSatoshi OkamotoKatsumi TeraiNaoji OkumuraKazuhito Tanaka
    • Yutaka NioSatoshi OkamotoKatsumi TeraiNaoji OkumuraKazuhito Tanaka
    • G06K940
    • H04N19/865H04N19/527H04N19/80H04N19/86
    • A vertical HPF and a horizontal HPF receive a video signal 101, and extract only a high frequency component in the vertical/horizontal directions, respectively. Absolute value taking parts take an absolute value of the high frequency components, respectively, and change their values to positive values. A horizontal accumulating/adding part and a vertical accumulating/adding part accumulate/add an input signal so as to output a vertical one-dimensional signal and a horizontal one-dimensional signal, respectively, each periodically having a peak value in the respective vertical and horizontal directions. A horizontal peak detecting part detects a horizontal peak position according to the horizontal one-dimensional signal. A vertical peak detecting part detects a vertical peak position according to the vertical one-dimensional signal and identifies a format thereof. A binarization part obtains a block boundary image, according to the horizontal peak position and the vertical peak position, in which pixel positions having a peak are provided with 1 and remaining pixel positions are provided with 0. In this manner, even if a block boundary to eliminate block noise thereon is not clearly identified, it becomes possible to correctly detect and eliminate the block boundary.
    • 垂直HPF和水平HPF接收视频信号101,并且仅分别在垂直/水平方向提取高频分量。 绝对值取零件分别取高频分量的绝对值,并将它们的值改为正值。 水平累积/加法部分和垂直累积/相加部分分别累积/加入输入信号,以分别输出垂直一维信号和水平一维信号,每个信号周期性地具有在垂直方向上的峰值, 水平方向。 水平峰值检测部根据水平一维信号检测水平峰值位置。 垂直峰值检测部分根据垂直一维信号检测垂直峰值位置并识别其格式。 二值化部分根据水平峰值位置和垂直峰值位置获得块边界图像,其中具有峰值的像素位置为1,并且剩余像素位置被设置为0.以这种方式,即使块边界 为了消除其上的块噪声没有被清楚地识别,可以正确地检测和消除块边界。
    • 6. 发明授权
    • Image display and horizontal speed modulator
    • 图像显示和水平速度调制器
    • US06529176B1
    • 2003-03-04
    • US09673361
    • 2000-10-16
    • Naoji OkumuraHiroki MontaHideyo UwabataYutaka NioKazuto TanakaYutaka Nishikawa
    • Naoji OkumuraHiroki MontaHideyo UwabataYutaka NioKazuto TanakaYutaka Nishikawa
    • G09G108
    • H04N5/44504H04N3/30H04N21/42653
    • A video signal processing circuit synthesizes a video signal and a graphic signal on the basis of a display switching control signal, inverts a synthesized signal on the time axis for each of a forward scanning period and a backward scanning period, and output a display signal. A speed modulating signal control circuit inverts the binarized display switching control signal on the time axis for each of the forward scanning period and the backward scanning period, expands the pulse width thereof, and feeds the display switching control signal to a speed modulating signal generating circuit. The speed modulating signal generating circuit subjects a display signal to first-order differentiation, inverts the polarity of a differentiated signal in the backward scanning signal, sets a portion, corresponding to the graphic signal, in the differentiated signal on the basis of the display switching control signal at a zero level, and generates a speed modulating signal.
    • 视频信号处理电路根据显示切换控制信号合成视频信号和图形信号,在正向扫描期间和后退扫描周期中的每个正反转扫描期间对时间轴上的合成信号进行反转,并输出显示信号。 速度调制信号控制电路在正向扫描周期和反向扫描期间中的每一个上对时间轴上的二值化显示切换控制信号进行反转,扩大其脉冲宽度,并将显示切换控制信号馈送到速度调制信号发生电路 。 速度调制信号发生电路对显示信号进行一阶微分,使反向扫描信号中的微分信号的极性反转,根据显示切换在微分信号中设定与图形信号对应的部分 控制信号为零电平,并产生速度调制信号。
    • 9. 发明授权
    • Video signal format converter
    • 视频信号格式转换器
    • US6020927A
    • 2000-02-01
    • US95615
    • 1998-06-10
    • Kazuhito TanakaYutaka Nio
    • Kazuhito TanakaYutaka Nio
    • H04N7/01
    • H04N7/0125
    • A video signal converter converts a first video signal into a second video signal by changing the number of scanning lines. A horizontal pulse synchronized with the first video signal is fed into a PLL circuit, which generates a first clock signal synchronized with the horizontal pulse. The first video signal undergoes A/D conversion by sampling with the first clock signal. The converter receives a first digital video signal which has undergone the A/D conversion, the first clock signal, the horizontal pulse, and a vertical pulse synchronized with the first video signal, and thus changes a number of scanning lines of the first video signal. The converter, next, writes a second digital video signal into a memory by synchronizing the first clock signal. Then, the second digital video signal is read out from the memory by synchronizing a second clock signal generated from another clock signal generator, and is outputted as a third digital video signal, which is converted by a D/A converter into a second video signal having a desirable number of scanning lines and being outputted without video distortion in the horizontal direction.
    • 视频信号转换器通过改变扫描行数将第一视频信号转换成第二视频信号。 与第一视频信号同步的水平脉冲被馈送到PLL电路,其产生与水平脉冲同步的第一时钟信号。 第一个视频信号通过采用第一个时钟信号进行A / D转换。 转换器接收经过A / D转换的第一数字视频信号,第一时钟信号,水平脉冲和与第一视频信号同步的垂直脉冲,从而改变第一视频信号的扫描行数 。 接下来,转换器通过同步第一时钟信号将第二数字视频信号写入存储器。 然后,通过同步由另一时钟信号发生器产生的第二时钟信号从存储器中读出第二数字视频信号,并将其作为第三数字视频信号输出,该第三数字视频信号由D / A转换器转换成第二视频信号 具有期望数量的扫描线,并且在水平方向上输出没有视频失真。
    • 10. 发明授权
    • Signal transmission system
    • 信号传输系统
    • US07394854B2
    • 2008-07-01
    • US10088468
    • 2001-07-23
    • Toshiro NishioYutaka Nio
    • Toshiro NishioYutaka Nio
    • H04N7/12H04N11/02H04N11/04H04B1/66
    • H04N19/00533H04N11/042H04N19/44
    • A signal transmission system: that includes a signal transmission unit (101) that includes a MPEG decoder (102), which receives digital broadcasting and outputs a luminance signal Y and two color difference signals PB/PR, and a transmission path encoding circuit (103), which encodes the YPBPR outputted from the MPEG decoder (102) into signals in the forms suited to a transmission path and transmits the encoded signals; and a signal reception unit (104) that includes a transmission path decoding circuit (105), which receives the encoded YPBPR and decodes them, a Y processing circuit (106), which processes the decoded luminance signal Y, a chrominance processing circuit (107), which processes the respective decoded color difference signals PB/PR, a signal conversion circuit (108), which converts the YPBPR outputted from the Y processing circuit (106) and the chrominance processing circuit (107) into RGB signals, and a display device (108) which displays the RGB signals.
    • 一种信号传输系统,包括:信号传输单元(101),包括MPEG解码器(102),其接收数字广播并输出亮度信号Y和两个色差信号P SUB B / 和传送路径编码电路(103),其将从MPEG解码器(102)输出的YP SUB B R SUB编码为信号 适合于传输路径并发送编码信号的形式; 以及信号接收单元(104),其包括传输路径解码电路(105),该传输路径解码电路(105)接收编码的YP< B> P< R>并对其进行解码,Y处理电路 106),其处理解码的亮度信号Y,处理各个解码的色差信号P SUB B / P SUB R的色度处理电路(107),信号转换 电路(108)将从Y处理电路(106)和色度处理电路(107)输出的YP B R SUB转换成RGB信号,显示 显示RGB信号的装置(108)。