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1. 发明授权

US06777248B1 Dielectric element and manufacturing method therefor 失效
标题翻译：介电元件及其制造方法
公开(公告)号：US06777248B1
公开(公告)日：2004-08-17
申请号：US09554116
申请日：2000-05-10
申请人： Toshihide Nabatame , Takaaki Suzuki , Kazutoshi Higashiyama , Tomoji Oishi
发明人： Toshihide Nabatame , Takaaki Suzuki , Kazutoshi Higashiyama , Tomoji Oishi
IPC分类号： H01L2100
CPC分类号： H01L28/55 , H01G4/1227 , H01G4/1245 , H01L21/31691 , H01L29/516
摘要： A ferroelectric element having a high Pr and a low Ec and having a good withstand voltage, which is in the form of a thin film using a ferroelectric layer containing insulating particles, is provided. The ferroelectric layer containing the insulating particles is effective to suppress leakage current caused through grain boundaries of crystals, and hence to exhibit a high Pr and a low Ec and a good withstand voltage. The ferroelectric element has a structure in which such a ferroelectric layer in the form of a thin film is sandwiched between electrodes. By incorporating the ferroelectric element in a field effect transistor structure, it is possible to realize a highly integrated semiconductor device for detecting reading or writing.
摘要翻译：提供具有高Pr和低Ec并且具有良好耐受电压的铁电体元件，其为使用含有绝缘颗粒的铁电层的薄膜形式。含有绝缘粒子的铁电体层能够有效地抑制由晶体晶界引起的漏电流，因此具有高的Pr和低的Ec以及良好的耐受电压。铁电元件具有这样的结构，其中这种薄膜形式的铁电层被夹在电极之间。通过将铁电元件结合在场效应晶体管结构中，可以实现用于检测读取或写入的高度集成的半导体器件。

2. 发明授权

US06198119B1 Ferroelectric element and method of producing the same 失效
标题翻译：铁电元件及其制造方法
公开(公告)号：US06198119B1
公开(公告)日：2001-03-06
申请号：US08814382
申请日：1997-03-11
申请人： Toshihide Nabatame , Takaaki Suzuki , Tomoji Oishi , Ken Takahashi , Kunihiro Maeda
发明人： Toshihide Nabatame , Takaaki Suzuki , Tomoji Oishi , Ken Takahashi , Kunihiro Maeda
IPC分类号： H01L2922
CPC分类号： H01L28/55 , H01L21/02197 , H01L21/02266 , H01L21/31691
摘要： A ferroelectric element is provided that can be highly densely integrated having a high Pr and a small Ec by using a ferroelectric thin film of the perovskite structure. A large distortion is imparted to the crystalline lattices of a ferroelectric thin film of the perovskite structure by using in combination elements having dissimilar ionic radii for the A-site that constitutes crystalline lattices, for the B-site and for the C-site that produces polarization, in order to obtain a ferroelectric element of a structure in which the ferroelectric thin film exhibiting a high spontaneous polarization and a small coersive electric field is sandwiched by the electrodes.
摘要翻译：提供通过使用钙钛矿结构的铁电薄膜，可以高密度地集成具有高Pr和小Ec的铁电元件。通过使用具有不同离子半径的组合元素，对于构成晶格的A位点，对于B位点和产生C位的C位，赋予钙钛矿结构的铁电薄膜的晶格大的变形为了获得其中由电极夹持表现出高自发极化和小的强电场的铁电薄膜的结构的铁电元件。

3. 发明授权

US06917065B2 Ferroelectric capacitor and semiconductor device 失效
标题翻译：铁电电容器和半导体器件
公开(公告)号：US06917065B2
公开(公告)日：2005-07-12
申请号：US10681173
申请日：2003-10-09
申请人： Tetsuo Fujiwara , Toshihide Nabatame , Takaaki Suzuki , Kazutoshi Higashiyama
发明人： Tetsuo Fujiwara , Toshihide Nabatame , Takaaki Suzuki , Kazutoshi Higashiyama
IPC分类号： H01L21/00 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115 , H01L29/06 , H01L29/76 , H01L31/062
CPC分类号： H01L27/11502 , H01L27/10805 , H01L27/1085 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A ferroelectric capacitor of the type having a top electrode, a ferroelectric thin film, and a bottom electrode, is characterized in that said ferroelectric thin film is a perovskite-type oxide containing Pb and said upper and bottom electrodes contain an intermetallic compound composed of Pt and Pb. An electronic device is provided with said ferroelectric capacitor. This construction is designed to solve the following problems. In a non-volatile ferroelectric memory (FeRAM), a degraded layer occurs near the interface between the PZT and the electrode due to hydrogen evolved during processing or due to diffusion of Pb from the PZT into the electrode. A stress due to a difference in lattice constant occurs in the interface between the electrode and the ferroelectric thin film. The degraded layer and the interfacial stress deteriorate the initial polarizing characteristics of the ferroelectric capacitor and also greatly deteriorate the polarizing characteristics after switching cycles.
摘要翻译：具有顶电极，铁电薄膜和底电极的铁电电容器的特征在于，所述铁电薄膜是含有Pb的钙钛矿型氧化物，所述上下电极含有由Pt构成的金属间化合物和铅。电子设备设有所述铁电电容器。这种结构旨在解决以下问题。在非易失性铁电存储器（FeRAM）中，由于在处理期间释放的氢或由于PZT向电极扩散Pb而在PZT和电极之间的界面附近出现劣化层。在电极和铁电薄膜之间的界面产生由于晶格常数的差异引起的应力。劣化层和界面应力劣化铁电电容器的初始极化特性，并且在开关周期后极大地降低极化特性。

4. 发明授权

US06548342B1 Method of producing oxide dielectric element, and memory and semiconductor device using the element 失效
标题翻译：生产氧化物介质元件的方法以及使用该元件的存储器和半导体器件
公开(公告)号：US06548342B1
公开(公告)日：2003-04-15
申请号：US09242302
申请日：1999-02-12
申请人： Takaaki Suzuki , Toshihide Nabatame , Kazutoshi Higashiyama
发明人： Takaaki Suzuki , Toshihide Nabatame , Kazutoshi Higashiyama
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/3165 , H01L28/55 , H01L29/51 , H01L29/516
摘要： The temperature at which an oxide dielectric thin film is formed can be made lower than conventional by reducing the concentration of oxygen in an atmosphere for forming the thin film. As a result, there can be formed an oxide dielectric thin film which has a crystal structure preferentially oriented at a crystal plane allowing a polarization axis to be directed in the vertical direction, which eliminates any reaction with an electrode material, and controls the growth of crystal grains. The use of such an oxide dielectric thin film can provide an oxide dielectric element having a high spontaneous polarization and a small coercive field. Consequently, it is possible to achieve a dielectric element having a high density of integration for detecting reading and writing operations, and a semiconductor device using the same.
摘要翻译：通过降低用于形成薄膜的气氛中的氧浓度，可以使形成氧化物电介质薄膜的温度低于常规温度。结果，可以形成氧化物电介质薄膜，该氧化物电介质薄膜的晶体结构在晶面优先取向，允许偏振轴在垂直方向上被引导，从而消除与电极材料的任何反应，并且控制生长晶粒。使用这样的氧化物电介质薄膜可以提供具有高自发极化和小的矫顽场的氧化物介电元件。因此，可以实现用于检测读写操作的高集成度的电介质元件和使用该电介质元件的半导体器件。

5. 发明授权

US07071053B2 Method of forming capacitor with ruthenium top and bottom electrodes by MOCVD 失效
标题翻译：通过MOCVD形成具有钌顶部和底部电极的电容器的方法
公开(公告)号：US07071053B2
公开(公告)日：2006-07-04
申请号：US10852121
申请日：2004-05-25
申请人： Toshihide Nabatame , Takaaki Suzuki , Tetsuo Fujiwara , Kazutoshi Higashiyama
发明人： Toshihide Nabatame , Takaaki Suzuki , Tetsuo Fujiwara , Kazutoshi Higashiyama
IPC分类号： H01L21/8242
CPC分类号： H01L28/55 , C23C16/18 , C23C16/40 , H01L28/60
摘要： A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.
摘要翻译：提供一种半导体器件，其包含对于高集成度的高纵横比的器件结构具有优异的阶梯覆盖的介电电容器及其制造方法。通过形成底部电极46和顶部电极48来制造高集成度的介电电容器，该底部电极46和顶部电极48包括具有100％阶梯覆盖的均匀的薄Ru膜，同时将电介质47放置在具有三维结构的基板44,45上，通过使用环戊二烯基络合物的MOCVD法在180℃以上至250℃以下的温度范围内的纵横比为3以上。

6. 发明授权

US06821845B1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06821845B1
公开(公告)日：2004-11-23
申请号：US09806861
申请日：2001-04-05
申请人： Toshihide Nabatame , Takaaki Suzuki , Tetsuo Fujiwara , Kazutoshi Higashiyama
发明人： Toshihide Nabatame , Takaaki Suzuki , Tetsuo Fujiwara , Kazutoshi Higashiyama
IPC分类号： H01L218242
CPC分类号： H01L28/55 , C23C16/18 , C23C16/40 , H01L28/60
摘要： A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.
摘要翻译：提供一种半导体器件，其包含对于高集成度的高纵横比的器件结构具有优异的阶梯覆盖的介电电容器及其制造方法。通过形成底部电极46和顶部电极48来制造高集成度的介电电容器，底部电极46和顶部电极48包括具有100％台阶覆盖率的均匀的薄Ru膜，同时将电介质47放置在具有三维结构的基板44,45上，通过使用环戊二烯基络合物的MOCVD法在180℃以上至250℃以下的温度范围内的纵横比为3以上。

7. 发明授权

US06483167B1 Semiconductor device and production method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06483167B1
公开(公告)日：2002-11-19
申请号：US09644716
申请日：2000-08-23
申请人： Toshihide Nabatame , Masaru Kadoshima , Takaaki Suzuki , Tetsuo Fujiwara , Seiji Watahiki , Yasuhiko Murata , Mitsuo Hayashibara
发明人： Toshihide Nabatame , Masaru Kadoshima , Takaaki Suzuki , Tetsuo Fujiwara , Seiji Watahiki , Yasuhiko Murata , Mitsuo Hayashibara
IPC分类号： H01L2900
CPC分类号： H01L28/60 , H01L28/55 , H01L28/91
摘要： In a semiconductor device and production method thereof, a technique is used to prevent film separation of the bottom electrode occurring during a heat treatment process which is carried out to make the bottom electrode closely packed and in the heat treatment process for producing dielectric crystallization. In the production method, a glue layer including an insulator is formed between SiO2 insulation layer and the inner wall of a concave hole. The SiO2 layer 14 is located on the Si board 11, and Si plug 12 and a barrier layer 13 are formed therein. A glue layer 16 is formed on the inner wall of the hole of the SiO2 insulation layer 15, and a bottom electrode 17 comprising Ru is formed on the barrier layer 13 and glue layer 16. Dielectric film 18 comprising BST and a top electrode 19 comprising Ru are laminated sequentially on the bottom electrode 17, to form a dielectric device with the bottom electrode 17.
摘要翻译：在半导体装置及其制造方法中，使用这样的技术来防止在进行底部电极紧密堆积的热处理过程中发生的底部电极的膜分离和用于产生电介质结晶的热处理工艺。在制造方法中，在SiO2绝缘层和凹孔的内壁之间形成包含绝缘体的胶层。 SiO 2层14位于Si基板11上，形成Si塞12和阻挡层13。在SiO 2绝缘层15的孔的内壁上形成胶层16，在阻挡层13和胶层16上形成包含Ru的底部电极17.包含BST的电介质膜18和顶部电极19包括 Ru依次层叠在底部电极17上，形成具有底部电极17的电介质器件。

8. 发明授权

US07772678B2 Metallic compound thin film that contains high-k dielectric metal, nitrogen, and oxygen 有权
标题翻译：含有高k电介质金属，氮和氧的金属化合物薄膜
公开(公告)号：US07772678B2
公开(公告)日：2010-08-10
申请号：US12333577
申请日：2008-12-12
申请人： Kunihiko Iwamoto , Koji Tominaga , Toshihide Nabatame , Tomoaki Nishimura
发明人： Kunihiko Iwamoto , Koji Tominaga , Toshihide Nabatame , Tomoaki Nishimura
IPC分类号： H01L23/58 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/28185 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an O2 atmosphere. By annealing the film in an O2 atmosphere at a temperature higher than 650° C., the leak current in the metal oxide film is controlled.
摘要翻译：在清洁基板的表面之后，形成界面层或反扩散膜。在抗扩散膜上构建金属氧化物膜。在NH 3气氛中进行退火，以便在金属氧化物膜中扩散氮。金属氧化物膜的构建和氮的扩散重复几次，随后在O 2气氛中进行退火。通过在高于650℃的温度下在O 2气氛中退火该膜，可以控制金属氧化物膜中的漏电流。

9. 发明授权

US07618855B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07618855B2
公开(公告)日：2009-11-17
申请号：US11540506
申请日：2006-10-02
申请人： Masaru Kadoshima , Toshihide Nabatame
发明人： Masaru Kadoshima , Toshihide Nabatame
IPC分类号： H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/6659
摘要： A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. Then, after a silicon oxide film is formed so as to cover the silicon gate electrodes, a surface of the silicon oxide film is polished by CMP, thereby exposing the surface of the silicon gate electrodes. Subsequently, a patterned insulating film is formed on the silicon oxide film. Thereafter, an adhesion film is formed on the silicon oxide film and the insulating film. Then, a nickel film is formed on the adhesion film. Thereafter, a silicide reaction is caused to occur between the silicon gate electrode and the nickel film via the adhesion film.
摘要翻译：一种能够通过由金属硅化物膜形成的栅电极在MISFET的制造工艺中提高产量的技术。在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成由多晶硅膜形成的硅栅电极。然后，在形成氧化硅膜以覆盖硅栅电极之后，通过CMP抛光氧化硅膜的表面，从而暴露硅栅电极的表面。随后，在氧化硅膜上形成图案化的绝缘膜。此后，在氧化硅膜和绝缘膜上形成粘合膜。然后，在粘合膜上形成镍膜。此后，通过粘合膜在硅栅电极和镍膜之间发生硅化物反应。

10. 发明授权

US07586755B2 Electronic circuit component 有权
标题翻译：电子电路元件
公开(公告)号：US07586755B2
公开(公告)日：2009-09-08
申请号：US11834452
申请日：2007-08-06
申请人： Toshiya Satoh , Masahiko Ogino , Takao Miwa , Takashi Naitou , Takashi Namekawa , Toshihide Nabatame , Shigehisa Motowaki
发明人： Toshiya Satoh , Masahiko Ogino , Takao Miwa , Takashi Naitou , Takashi Namekawa , Toshihide Nabatame , Shigehisa Motowaki
IPC分类号： H05K7/00
CPC分类号： H01L27/13 , H01F17/0006 , H01L23/49822 , H01L23/49827 , H01L27/016 , H01L27/0676 , H01L27/08 , H01L2224/16 , H01L2924/01021 , H01L2924/01025 , H01L2924/01057 , H01L2924/01063 , H01L2924/01066 , H01L2924/01067 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/19011 , H01L2924/3011 , H01L2924/3025 , H05K1/16 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/28 , H05K3/3457 , H05K3/4602 , H05K3/4644 , H05K2201/09536 , H05K2201/09827 , H01L2924/00
摘要： Through an improvement of module size increase due to mounting a single passive element on a substrate and an increase in the mounting cost, to provide a highly reliable, high performance and small sized electronic circuit component which permits to integrate a variety of electronic parts such as capacitors, inductors and resistors in a high density with low cost.The electronic circuit component comprises an insulator substrate, a plurality of electrodes having different areas provided on the insulator substrate, one or more elements selected from a capacitor element of dielectric material sandwiched between the electrodes, an inductor element and resistor element, a metal wiring connecting the elements, a metal terminal part of a part of the metal wiring and an organic insulator material covering the elements and the circumference of the metal wiring portion excluding the metal terminal portion.
摘要翻译：通过在基板上安装单个无源元件并增加安装成本来改善模块尺寸增加，提供高可靠性，高性能和小尺寸的电子电路元件，其允许将各种电子部件如电容器，电感器和电阻器，高密度，低成本。电子电路部件包括绝缘体基板，设置在绝缘体基板上的具有不同区域的多个电极，选自被夹在电极之间的电介质材料的电容器元件中的一个或多个元件，电感元件和电阻元件，连接所述元件，所述金属布线的一部分的金属端子部分和覆盖所述元件的有机绝缘体材料以及除了所述金属端子部分之外的所述金属布线部分的周边。

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