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1. 发明授权

US07898045B2 Passive electrically testable acceleration and voltage measurement devices 有权
标题翻译：被动电气可测加速度和电压测量装置
公开(公告)号：US07898045B2
公开(公告)日：2011-03-01
申请号：US12166623
申请日：2008-07-02
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Leah Marie Pfeifer Pastel
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Leah Marie Pfeifer Pastel
IPC分类号： H01L29/84
CPC分类号： G01P15/0802 , B82Y15/00 , G01P15/06 , G01P15/0891 , G01P15/135 , H01H1/0094 , H01H35/14
摘要： Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to the nanotubes.
摘要翻译：加速度和电压测量装置以及制造加速度和电压测量装置的方法。所述加速和电压测量装置包括在第一绝缘层的顶表面上的导电板; 在所述导电板的顶表面上的第二绝缘层，所述板的顶表面暴露在所述第二绝缘层的开口中; 导电纳米管悬挂在开口处，并且与纳米管的导电接触。

2. 发明授权

US07629192B2 Passive electrically testable acceleration and voltage measurement devices 失效
标题翻译：被动电气可测加速度和电压测量装置
公开(公告)号：US07629192B2
公开(公告)日：2009-12-08
申请号：US11161181
申请日：2005-10-13
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Leah Marie Pfeifer Pastel
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Leah Marie Pfeifer Pastel
IPC分类号： H01L21/00
CPC分类号： G01P15/0802 , B82Y15/00 , G01P15/06 , G01P15/0891 , G01P15/135 , H01H1/0094 , H01H35/14
摘要： Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to the nanotubes.
摘要翻译：加速度和电压测量装置以及制造加速度和电压测量装置的方法。所述加速和电压测量装置包括在第一绝缘层的顶表面上的导电板; 在所述导电板的顶表面上的第二绝缘层，所述板的顶表面暴露在所述第二绝缘层的开口中; 导电纳米管悬挂在开口处，并且与纳米管的导电接触。

3. 发明申请

US20080258246A1 PASSIVE ELECTRICALLY TESTABLE ACCELERATION AND VOLTAGE MEASUREMENT DEVICES 有权
标题翻译：被动电气测试加速和电压测量装置
公开(公告)号：US20080258246A1
公开(公告)日：2008-10-23
申请号：US12166623
申请日：2008-07-02
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger , Leah Marie Pfeifer Pastel
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger , Leah Marie Pfeifer Pastel
IPC分类号： H01L29/84
CPC分类号： G01P15/0802 , B82Y15/00 , G01P15/06 , G01P15/0891 , G01P15/135 , H01H1/0094 , H01H35/14
摘要： Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to said nanotubes.
摘要翻译：加速度和电压测量装置以及制造加速度和电压测量装置的方法。所述加速和电压测量装置包括在第一绝缘层的顶表面上的导电板; 在所述导电板的顶表面上的第二绝缘层，所述板的顶表面暴露在所述第二绝缘层的开口中; 导电纳米管悬挂在开口上，并与导电接触到所述纳米管。

4. 发明授权

US07971176B2 Method for testing integrated circuits 有权
标题翻译：集成电路测试方法
公开(公告)号：US07971176B2
公开(公告)日：2011-06-28
申请号：US12050207
申请日：2008-03-18
申请人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
IPC分类号： G06F17/50 , G06F11/22 , G06F19/00
CPC分类号： G01R31/31835
摘要： A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.
摘要翻译：一种集成电路测试方法。该方法包括选择集成电路的网络和设备的一组物理特征，集成电路具有由网络连接的模式输入点和模式观察点，每个网络由输入点定义，并且所有扇出路径到（ i）网的其他网的输入点或（ii）到模式观察点; 为特征集合中的每个特征选择测量单元; 基于每个网络的每个扇出路径的每个段中的特征的测量单元的数量，为每个扇出路径的每个段分配权重; 以及基于分配给集成电路的每个网络的每个段的权重，生成针对测试覆盖和成本优化的一组测试模式。

5. 发明申请

US20110214102A1 METHOD FOR TESTING INTEGRATED CIRCUITS 有权
标题翻译：测试集成电路的方法
公开(公告)号：US20110214102A1
公开(公告)日：2011-09-01
申请号：US13102249
申请日：2011-05-06
申请人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
IPC分类号： G06F17/50
CPC分类号： G01R31/31835
摘要： A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.
摘要翻译：一种集成电路测试方法。该方法包括选择集成电路的网络和设备的一组物理特征，集成电路具有由网络连接的模式输入点和模式观察点，每个网络由输入点定义，并且所有扇出路径到（ i）网的其他网的输入点或（ii）到模式观察点; 为特征集合中的每个特征选择测量单元; 基于每个网络的每个扇出路径的每个段中的特征的测量单元的数量，为每个扇出路径的每个段分配权重; 以及基于分配给集成电路的每个网络的每个段的权重，生成针对测试覆盖和成本优化的一组测试模式。

6. 发明授权

US07870519B2 Method for determining features associated with fails of integrated circuits 有权
标题翻译：确定与集成电路故障相关的特征的方法
公开(公告)号：US07870519B2
公开(公告)日：2011-01-11
申请号：US11941998
申请日：2007-11-19
申请人： Rao H. Desineni , Maroun Kassab , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Leah Marie Pfeifer Pastel
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G01R31/318342
摘要： A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; identifying pattern observation points for each signal path of the subset of signal paths; selecting a set of features associated with the integrated circuit design; applying a set of test patterns to one or more integrated circuit chips; determining failing signal paths of the subset of signal paths for each integrated circuit chip; mapping failing signal paths of the subset of signal paths to the set of features to generate a correspondence between the failing signal paths and the features; and analyzing the correspondence and identifying suspect features of the set of features based on the analyzing.
摘要翻译：一种用于测试集成电路并分析测试数据的方法。该方法包括：定义一组信号路径选择标准; 选择集成电路设计的信号路径的子集，所述选择信号路径满足选择标准; 识别信号路径子集的每个信号路径的模式观察点; 选择与集成电路设计相关的一组特征; 将一组测试图案应用于一个或多个集成电路芯片; 确定每个集成电路芯片的信号路径子集的失败信号路径; 将所述信号路径子集的故障信号路径映射到所述特征集合，以产生所述故障信号路径和所述特征之间的对应关系; 并基于分析，分析对应关系并识别该组特征的可疑特征。

7. 发明授权

US08136082B2 Method for testing integrated circuits 有权
标题翻译：集成电路测试方法
公开(公告)号：US08136082B2
公开(公告)日：2012-03-13
申请号：US13102249
申请日：2011-05-06
申请人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
IPC分类号： G06F17/50 , G06F11/22 , G06F19/00
CPC分类号： G01R31/31835
摘要： A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.
摘要翻译：一种集成电路测试方法。该方法包括选择集成电路的网络和设备的一组物理特征，集成电路具有由网络连接的模式输入点和模式观察点，每个网络由输入点定义，并且所有扇出路径到（ i）网的其他网的输入点或（ii）到模式观察点; 为特征集合中的每个特征选择测量单元; 基于每个网络的每个扇出路径的每个段中的特征的测量单元的数量，为每个扇出路径的每个段分配权重; 以及基于分配给集成电路的每个网络的每个段的权重，生成针对测试覆盖和成本优化的一组测试模式。

8. 发明申请

US20090240458A1 METHOD FOR TESTING INTEGRATED CIRCUITS 有权
标题翻译：测试集成电路的方法
公开(公告)号：US20090240458A1
公开(公告)日：2009-09-24
申请号：US12050207
申请日：2008-03-18
申请人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
IPC分类号： G01R31/00
CPC分类号： G01R31/31835
摘要： A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.
摘要翻译：一种集成电路测试方法。该方法包括选择集成电路网络和设备的一组物理特征，集成电路具有由网络连接的模式输入点和模式观察点，每个网络由输入点定义，并且所有扇出路径到（ i）网的其他网的输入点或（ii）到模式观察点; 为特征集合中的每个特征选择测量单元; 基于每个网络的每个扇出路径的每个段中的特征的测量单元的数量，为每个扇出路径的每个段分配权重; 以及基于分配给集成电路的每个网络的每个段的权重，生成针对测试覆盖和成本优化的一组测试模式。

9. 发明申请

US20090132976A1 METHOD FOR TESTING AN INTEGRATED CIRCUIT AND ANALYZING TEST DATA 有权
标题翻译：用于测试集成电路和分析测试数据的方法
公开(公告)号：US20090132976A1
公开(公告)日：2009-05-21
申请号：US11941998
申请日：2007-11-19
申请人： Rao H. Desineni , Maroun Kassab , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Leah Marie Pfeifer Pastel
IPC分类号： G06F17/50
CPC分类号： G01R31/318342
摘要： A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; identifying pattern observation points for each signal path of the subset of signal paths; selecting a set of features associated with the integrated circuit design; applying a set of test patterns to one or more integrated circuit chips; determining failing signal paths of the subset of signal paths for each integrated circuit chip; mapping failing signal paths of the subset of signal paths to the set of features to generate a correspondence between the failing signal paths and the features; and analyzing the correspondence and identifying suspect features of the set of features based on the analyzing.
摘要翻译：一种用于测试集成电路并分析测试数据的方法。该方法包括：定义一组信号路径选择标准; 选择集成电路设计的信号路径的子集，所述选择信号路径满足选择标准; 识别信号路径子集的每个信号路径的模式观察点; 选择与集成电路设计相关的一组特征; 将一组测试图案应用于一个或多个集成电路芯片; 确定每个集成电路芯片的信号路径子集的失败信号路径; 将所述信号路径子集的故障信号路径映射到所述特征集合，以产生所述故障信号路径和所述特征之间的对应关系; 并基于分析，分析对应关系并识别该组特征的可疑特征。

10. 发明授权

US07007214B2 Diagnosable scan chain 有权
标题翻译：诊断扫描链
公开(公告)号：US07007214B2
公开(公告)日：2006-02-28
申请号：US10604194
申请日：2003-06-30
申请人： Steven Michael Eustis , Leah Marie Pfeifer Pastel , Thomas Richard Bednar , Thomas Gregory Sopchak , Jeffery Howard Oppold
发明人： Steven Michael Eustis , Leah Marie Pfeifer Pastel , Thomas Richard Bednar , Thomas Gregory Sopchak , Jeffery Howard Oppold
IPC分类号： G01R31/28 , G06F7/02
CPC分类号： G01R31/31855
摘要： A method and system for locating connector defects in a defective scan chain that has a parallel non-defective scan chain on a different wiring level, with both scan chains being laid out in a regular array pattern. A predetermined bit sequence is scanned into the defective scan chain. The contents of the defective scan chain are then parallel shifted into the non-defective scan chain. The contents of the non-defective scan chain is then scanned out and compared with the predetermined bit sequence. The comparison of the scanned out bits with the predetermined bit sequence facilitates locating both physically and logically where a connector defect has occurred in the defective scan chain.
摘要翻译：一种用于定位不同扫描链中的连接器缺陷的方法和系统，所述缺陷扫描链在不同布线级上具有并联的无缺陷扫描链，其中两个扫描链以规则阵列图案布置。预定的位序列被扫描到有缺陷的扫描链中。然后将有缺陷的扫描链的内容平行移入无缺陷扫描链。然后将无缺陷扫描链的内容扫描出来并与预定比特序列进行比较。扫描出的比特与预定比特序列的比较便于在缺陷扫描链中发生连接器缺陷的物理和逻辑地定位。

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