专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07870519B2 Method for determining features associated with fails of integrated circuits 有权
标题翻译：确定与集成电路故障相关的特征的方法
公开(公告)号：US07870519B2
公开(公告)日：2011-01-11
申请号：US11941998
申请日：2007-11-19
申请人： Rao H. Desineni , Maroun Kassab , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Leah Marie Pfeifer Pastel
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G01R31/318342
摘要： A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; identifying pattern observation points for each signal path of the subset of signal paths; selecting a set of features associated with the integrated circuit design; applying a set of test patterns to one or more integrated circuit chips; determining failing signal paths of the subset of signal paths for each integrated circuit chip; mapping failing signal paths of the subset of signal paths to the set of features to generate a correspondence between the failing signal paths and the features; and analyzing the correspondence and identifying suspect features of the set of features based on the analyzing.
摘要翻译：一种用于测试集成电路并分析测试数据的方法。该方法包括：定义一组信号路径选择标准; 选择集成电路设计的信号路径的子集，所述选择信号路径满足选择标准; 识别信号路径子集的每个信号路径的模式观察点; 选择与集成电路设计相关的一组特征; 将一组测试图案应用于一个或多个集成电路芯片; 确定每个集成电路芯片的信号路径子集的失败信号路径; 将所述信号路径子集的故障信号路径映射到所述特征集合，以产生所述故障信号路径和所述特征之间的对应关系; 并基于分析，分析对应关系并识别该组特征的可疑特征。

2. 发明授权

US07971176B2 Method for testing integrated circuits 有权
标题翻译：集成电路测试方法
公开(公告)号：US07971176B2
公开(公告)日：2011-06-28
申请号：US12050207
申请日：2008-03-18
申请人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
IPC分类号： G06F17/50 , G06F11/22 , G06F19/00
CPC分类号： G01R31/31835
摘要： A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.
摘要翻译：一种集成电路测试方法。该方法包括选择集成电路的网络和设备的一组物理特征，集成电路具有由网络连接的模式输入点和模式观察点，每个网络由输入点定义，并且所有扇出路径到（ i）网的其他网的输入点或（ii）到模式观察点; 为特征集合中的每个特征选择测量单元; 基于每个网络的每个扇出路径的每个段中的特征的测量单元的数量，为每个扇出路径的每个段分配权重; 以及基于分配给集成电路的每个网络的每个段的权重，生成针对测试覆盖和成本优化的一组测试模式。

3. 发明申请

US20110214102A1 METHOD FOR TESTING INTEGRATED CIRCUITS 有权
标题翻译：测试集成电路的方法
公开(公告)号：US20110214102A1
公开(公告)日：2011-09-01
申请号：US13102249
申请日：2011-05-06
申请人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
IPC分类号： G06F17/50
CPC分类号： G01R31/31835
摘要： A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.
摘要翻译：一种集成电路测试方法。该方法包括选择集成电路的网络和设备的一组物理特征，集成电路具有由网络连接的模式输入点和模式观察点，每个网络由输入点定义，并且所有扇出路径到（ i）网的其他网的输入点或（ii）到模式观察点; 为特征集合中的每个特征选择测量单元; 基于每个网络的每个扇出路径的每个段中的特征的测量单元的数量，为每个扇出路径的每个段分配权重; 以及基于分配给集成电路的每个网络的每个段的权重，生成针对测试覆盖和成本优化的一组测试模式。

4. 发明授权

US08136082B2 Method for testing integrated circuits 有权
标题翻译：集成电路测试方法
公开(公告)号：US08136082B2
公开(公告)日：2012-03-13
申请号：US13102249
申请日：2011-05-06
申请人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
IPC分类号： G06F17/50 , G06F11/22 , G06F19/00
CPC分类号： G01R31/31835
摘要： A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.
摘要翻译：一种集成电路测试方法。该方法包括选择集成电路的网络和设备的一组物理特征，集成电路具有由网络连接的模式输入点和模式观察点，每个网络由输入点定义，并且所有扇出路径到（ i）网的其他网的输入点或（ii）到模式观察点; 为特征集合中的每个特征选择测量单元; 基于每个网络的每个扇出路径的每个段中的特征的测量单元的数量，为每个扇出路径的每个段分配权重; 以及基于分配给集成电路的每个网络的每个段的权重，生成针对测试覆盖和成本优化的一组测试模式。

5. 发明申请

US20090240458A1 METHOD FOR TESTING INTEGRATED CIRCUITS 有权
标题翻译：测试集成电路的方法
公开(公告)号：US20090240458A1
公开(公告)日：2009-09-24
申请号：US12050207
申请日：2008-03-18
申请人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Franco Motika , Leah Marie Pfeifer Pastel
IPC分类号： G01R31/00
CPC分类号： G01R31/31835
摘要： A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.
摘要翻译：一种集成电路测试方法。该方法包括选择集成电路网络和设备的一组物理特征，集成电路具有由网络连接的模式输入点和模式观察点，每个网络由输入点定义，并且所有扇出路径到（ i）网的其他网的输入点或（ii）到模式观察点; 为特征集合中的每个特征选择测量单元; 基于每个网络的每个扇出路径的每个段中的特征的测量单元的数量，为每个扇出路径的每个段分配权重; 以及基于分配给集成电路的每个网络的每个段的权重，生成针对测试覆盖和成本优化的一组测试模式。

6. 发明申请

US20090132976A1 METHOD FOR TESTING AN INTEGRATED CIRCUIT AND ANALYZING TEST DATA 有权
标题翻译：用于测试集成电路和分析测试数据的方法
公开(公告)号：US20090132976A1
公开(公告)日：2009-05-21
申请号：US11941998
申请日：2007-11-19
申请人： Rao H. Desineni , Maroun Kassab , Leah Marie Pfeifer Pastel
发明人： Rao H. Desineni , Maroun Kassab , Leah Marie Pfeifer Pastel
IPC分类号： G06F17/50
CPC分类号： G01R31/318342
摘要： A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; identifying pattern observation points for each signal path of the subset of signal paths; selecting a set of features associated with the integrated circuit design; applying a set of test patterns to one or more integrated circuit chips; determining failing signal paths of the subset of signal paths for each integrated circuit chip; mapping failing signal paths of the subset of signal paths to the set of features to generate a correspondence between the failing signal paths and the features; and analyzing the correspondence and identifying suspect features of the set of features based on the analyzing.
摘要翻译：一种用于测试集成电路并分析测试数据的方法。该方法包括：定义一组信号路径选择标准; 选择集成电路设计的信号路径的子集，所述选择信号路径满足选择标准; 识别信号路径子集的每个信号路径的模式观察点; 选择与集成电路设计相关的一组特征; 将一组测试图案应用于一个或多个集成电路芯片; 确定每个集成电路芯片的信号路径子集的失败信号路径; 将所述信号路径子集的故障信号路径映射到所述特征集合，以产生所述故障信号路径和所述特征之间的对应关系; 并基于分析，分析对应关系并识别该组特征的可疑特征。

7. 发明授权

US08566059B2 Insertion of faults in logic model used in simulation 失效
标题翻译：在模拟中使用的逻辑模型中插入故障
公开(公告)号：US08566059B2
公开(公告)日：2013-10-22
申请号：US12633151
申请日：2009-12-08
申请人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
发明人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
IPC分类号： G06F17/50 , G01R31/00
CPC分类号： G06F17/5022 , G06F11/261 , G06F2217/70
摘要： A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.
摘要翻译：一种基于集成电路（IC）布局的物理布局选择故障候选的方法，其包括：识别IC布局中的故障观察点，确定IC电路布局中的故障观察点接近度几何，确定接近度准则满足故障观测点，识别符合接近度标准的故障观测点相关故障; 并在故障候选集中包括识别的故障。

8. 发明授权

US07853848B2 System and method for signature-based systematic condition detection and analysis 失效
标题翻译：基于签名的系统状态检测和分析的系统和方法
公开(公告)号：US07853848B2
公开(公告)日：2010-12-14
申请号：US11875975
申请日：2007-10-22
申请人： Rao H. Desineni , Maroun Kassab , Leah M. Pastel
发明人： Rao H. Desineni , Maroun Kassab , Leah M. Pastel
IPC分类号： G01R31/28 , G01R31/30 , G01R31/26 , G01R31/08 , G06F17/50
CPC分类号： G01R31/318321
摘要： Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.
摘要翻译：公开了用于检测和分析在制造的装置中发生的系统状况的系统，方法和服务的实施例。每个实施例包括为多个被测试设备中的每一个产生唯一的签名。基于签名定义的初始集合以及至少部分地从选定的测试数据导出的那些签名定义的值来生成签名。基于签名之间的共同点检测系统条件。然后单独或与附加信息一起分析系统条件，以便开发设备之间的基本相似性列表。分析结果可用于通过修改签名定义集和/或通过修改数据选择来完善系统状态检测和分析过程。

9. 发明申请

US20090106614A1 SYSTEM AND METHOD FOR SIGNATURE-BASED SYSTEMATIC CONDITION DETECTION AND ANALYSIS 失效
标题翻译：用于基于签名的系统状态检测和分析的系统和方法
公开(公告)号：US20090106614A1
公开(公告)日：2009-04-23
申请号：US11875975
申请日：2007-10-22
申请人： Rao H. Desineni , Maroun Kassab , Leah M. Pastel
发明人： Rao H. Desineni , Maroun Kassab , Leah M. Pastel
IPC分类号： G01R31/3181 , G06F11/26
CPC分类号： G01R31/318321
摘要： Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.
摘要翻译：公开了用于检测和分析在制造的装置中发生的系统状况的系统，方法和服务的实施例。每个实施例包括为多个被测试设备中的每一个产生唯一的签名。基于签名定义的初始集合以及至少部分地从选定的测试数据导出的那些签名定义的值来生成签名。基于签名之间的共同点检测系统条件。然后单独或与附加信息一起分析系统条件，以便开发设备之间的基本相似性列表。分析结果可用于通过修改签名定义集和/或通过修改数据选择来完善系统状态检测和分析过程。

10. 发明申请

US20110137602A1 INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION 失效
标题翻译：在模拟中使用的逻辑模型中的故障插入
公开(公告)号：US20110137602A1
公开(公告)日：2011-06-09
申请号：US12633151
申请日：2009-12-08
申请人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
发明人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
IPC分类号： G01R31/14 , G06F17/50
CPC分类号： G06F17/5022 , G06F11/261 , G06F2217/70
摘要： A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.
摘要翻译：一种基于集成电路（IC）布局的物理布局选择故障候选的方法，其包括：识别IC布局中的故障观察点，确定IC电路布局中的故障观察点接近度几何，确定接近度准则满足故障观测点，识别符合接近度标准的故障观测点相关故障; 并在故障候选集中包括识别的故障。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式