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1. 发明申请

US20120241722A1 FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管
公开(公告)号：US20120241722A1
公开(公告)日：2012-09-27
申请号：US13240246
申请日：2011-09-22
申请人： Keiji Ikeda , Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka
发明人： Keiji Ikeda , Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka
IPC分类号： H01L29/165
CPC分类号： H01L29/4983 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/6656
摘要： A field effect transistor according to an embodiment includes: a semiconductor layer; a source region and a drain region formed at a distance from each other in the semiconductor layer; a gate insulating film formed on a portion of the semiconductor layer, the portion being located between the source region and the drain region; a gate electrode formed on the gate insulating film; and a gate sidewall formed on at least one of side faces of the gate electrode, the side faces being located on a side of the source region and on a side of the drain region, the gate sidewall being made of a high dielectric material. The source region and the drain region are separately-placed from the corresponding side faces of the gate electrode.
摘要翻译：根据实施例的场效应晶体管包括：半导体层; 在半导体层中形成为彼此相距一定距离的源极区域和漏极区域; 形成在半导体层的一部分上的栅极绝缘膜，该部分位于源极区域和漏极区域之间; 形成在栅极绝缘膜上的栅电极; 以及栅极侧壁，其形成在所述栅电极的至少一个侧面上，所述侧面位于所述源极区域的一侧，并且在所述漏极区域的侧面上，所述栅极侧壁由高介电材料制成。源极区域和漏极区域与栅电极的相应侧面分开设置。

2. 发明授权

US07619239B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07619239B2
公开(公告)日：2009-11-17
申请号：US11437730
申请日：2006-05-22
申请人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
发明人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L21/84 , H01L29/78687
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.
摘要翻译：半导体器件包括形成在绝缘层上的半导体层上的n沟道MIS晶体管和p沟道MIS晶体管，其中n沟道MIS晶体管的沟道由具有双轴拉伸应变的应变Si层形成， p沟道MIS晶体管的沟道由在沟道长度方向上具有单轴压缩应变的应变SiGe层形成。

3. 发明申请

US20060266996A1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US20060266996A1
公开(公告)日：2006-11-30
申请号：US11437730
申请日：2006-05-22
申请人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
发明人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
IPC分类号： H01L31/00
CPC分类号： H01L29/785 , H01L21/84 , H01L29/78687
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.

4. 发明申请

US20070241399A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070241399A1
公开(公告)日：2007-10-18
申请号：US11705450
申请日：2007-02-13
申请人： Toshifumi Irisawa , Toshinori Numata , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Toshinori Numata , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/7853 , H01L29/66636 , H01L29/66795 , H01L29/78687
摘要： In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.
摘要翻译：在包括在多个表面上具有沟道的多栅极MIS晶体管的半导体器件中，在绝缘膜上沿着给定方向形成的岛状半导体层的侧表面上的栅极绝缘膜上形成栅电极，并且源极/漏极形成为与半导体层接触。半导体层具有沿给定方向的多个侧表面。由相邻侧面形成的所有角度大于90°。垂直于给定方向的部分垂直和水平对称。

5. 发明申请

US20060170011A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060170011A1
公开(公告)日：2006-08-03
申请号：US11235168
申请日：2005-09-27
申请人： Toshifumi Irisawa , Toshinori Numata
发明人： Toshifumi Irisawa , Toshinori Numata
IPC分类号： H01L29/768
CPC分类号： H01L29/0649 , H01L29/42392 , H01L29/7849 , H01L29/78687
摘要： A semiconductor device includes a gate-all-around MOSFET structure comprises a first semiconductor layer which is formed on a support substrate and which has a recess formed on a surface thereof, a second semiconductor layer formed on the first semiconductor layer and which has a part thereof formed to cross over the recess of the first semiconductor layer, a gate electrode which is formed through a gate insulation film to surround the crossing portion of the second semiconductor layer and which has parts other than the part located under the second semiconductor layer processed in a gate pattern, source and drain areas formed on the second semiconductor layer, and a sidewall insulation film which is formed on sidewall surfaces of the recess of the first semiconductor layer and which has a greater thickness than the gate insulation film.
摘要翻译：半导体器件包括栅极全环MOSFET结构，其包括形成在支撑衬底上并具有形成在其表面上的凹部的第一半导体层，形成在第一半导体层上的第二半导体层，其形成为跨越所述第一半导体层的凹部，栅电极，其通过栅极绝缘膜形成以围绕所述第二半导体层的交叉部分，并且具有除了位于所述第二半导体层下方的部分以外的部分形成在第二半导体层上的栅极图案，源极和漏极区域以及形成在第一半导体层的凹部的侧壁表面上并且具有比栅极绝缘膜更大的厚度的侧壁绝缘膜。

6. 发明授权

US07622773B2 Semiconductor device including multi-gate metal-insulator-semiconductor (MIS) transistor 有权
标题翻译：包括多栅极金属 - 绝缘体 - 半导体（MIS）晶体管的半导体器件
公开(公告)号：US07622773B2
公开(公告)日：2009-11-24
申请号：US11705450
申请日：2007-02-13
申请人： Toshifumi Irisawa , Toshinori Numata , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Toshinori Numata , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L27/12
CPC分类号： H01L29/7853 , H01L29/66636 , H01L29/66795 , H01L29/78687
摘要： In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.
摘要翻译：在包括在多个表面上具有沟道的多栅极MIS晶体管的半导体器件中，在绝缘膜上沿着给定方向形成的岛状半导体层的侧表面上的栅极绝缘膜上形成栅电极，并且源极/漏极形成为与半导体层接触。半导体层具有沿给定方向的多个侧表面。由相邻侧面形成的所有角度大于90°。垂直于给定方向的部分垂直和水平对称。

7. 发明授权

US08932915B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08932915B2
公开(公告)日：2015-01-13
申请号：US13082103
申请日：2011-04-07
申请人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
发明人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
IPC分类号： H01L29/772 , H01L21/336 , B82Y10/00 , H01L21/84 , H01L27/06 , H01L27/115 , H01L27/12 , H01L29/04 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/792 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/66765 , B82Y10/00 , H01L21/823821 , H01L21/84 , H01L21/845 , H01L27/0688 , H01L27/092 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/0673 , H01L29/66439 , H01L29/66666 , H01L29/66833 , H01L29/775 , H01L29/7827 , H01L29/7843 , H01L29/7847 , H01L29/78669 , H01L29/78678 , H01L29/792
摘要： A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.
摘要翻译：实施例的半导体器件制造方法包括以下步骤：在半导体衬底上形成第一绝缘层; 在第一绝缘层上形成具有窄部分的非晶或多晶半导体层; 在所述半导体层上形成具有大于所述半导体层的热膨胀系数的热膨胀系数的第二绝缘层; 进行热处理; 去除所述第二绝缘层; 在所述窄部的侧面上形成栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 以及在所述半导体层中形成源 - 漏区。

8. 发明授权

US08669162B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08669162B2
公开(公告)日：2014-03-11
申请号：US13401478
申请日：2012-02-21
申请人： Yukio Nakabayashi , Toshinori Numata
发明人： Yukio Nakabayashi , Toshinori Numata
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/785
摘要： A method of manufacturing a semiconductor device according to an embodiment includes: forming a plurality of semiconductor layers located at a distance from one another on a first insulating film; forming a gate insulating film that covers both side faces and an upper face of each of the semiconductor layers; forming a gate electrode of a polysilicon film to cover the gate insulating film of each of the semiconductor layers; forming a second insulating film on an entire surface; exposing an upper face of the gate electrode by performing selective etching on a portion of the second insulating film; siliciding the gate electrode; and forming a stress applying film that applies a stress in a direction perpendicular to the extending direction of each of the semiconductor layers and parallel to an upper face of the first insulating film.
摘要翻译：根据实施例的制造半导体器件的方法包括：在第一绝缘膜上形成彼此间隔一定距离的多个半导体层; 形成覆盖所述半导体层的两个侧面和上表面的栅极绝缘膜; 形成多晶硅膜的栅电极以覆盖每个半导体层的栅极绝缘膜; 在整个表面上形成第二绝缘膜; 通过对所述第二绝缘膜的一部分进行选择性蚀刻来暴露所述栅电极的上表面; 硅化栅电极; 以及形成应力施加膜，所述应力施加膜在垂直于每个所述半导体层的延伸方向的方向上施加应力，并平行于所述第一绝缘膜的上表面。

9. 发明授权

US07592646B2 Semiconductor device with a SiGe layer having uniaxial lattice strain 有权
标题翻译：具有单晶晶格应变的SiGe层的半导体器件
公开(公告)号：US07592646B2
公开(公告)日：2009-09-22
申请号：US11389534
申请日：2006-03-27
申请人： Toshinori Numata
发明人： Toshinori Numata
IPC分类号： H01L29/165
CPC分类号： H01L29/78687
摘要： A semiconductor device includes a MIS transistor. The device includes a buried insulating film formed in one part of a substrate, the buried insulating film being elongated in a gate-width direction and shortened in a gate-length direction of the MIS transistor. A first semiconductor layer is formed on the buried insulating film and has uniaxial lattice strain. A second semiconductor layer covers both sides of the buried insulating film and both sides of the first semiconductor layer, the sides being opposite in the gate-length direction. A gate electrode is formed on the first semiconductor layer with a gate insulating film being formed between the gate electrode and the first semiconductor layer. A source region and a drain region are formed in the second semiconductor layer.
摘要翻译：半导体器件包括MIS晶体管。该器件包括形成在衬底的一部分中的掩埋绝缘膜，该掩埋绝缘膜在栅极宽度方向上延伸并且在MIS晶体管的栅极长度方向上缩短。在掩埋绝缘膜上形成第一半导体层，具有单轴晶格应变。第二半导体层覆盖掩埋绝缘膜的两侧和第一半导体层的两侧，两侧在栅极长度方向上相反。栅电极形成在第一半导体层上，栅极绝缘膜形成在栅电极和第一半导体层之间。在第二半导体层中形成源极区和漏极区。

10. 发明申请

US20060267046A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060267046A1
公开(公告)日：2006-11-30
申请号：US11389534
申请日：2006-03-27
申请人： Toshinori Numata
发明人： Toshinori Numata
IPC分类号： H01L31/00 , H01L21/336
CPC分类号： H01L29/78687
摘要： A semiconductor device with including a MIS transistor. The device comprises a buried insulating film formed in one part of a substrate, the buried insulating film being elongated in a gate-width direction and shortened in a gate-length direction of the MIS transistor, a first semiconductor layer formed on the buried insulating film and having uniaxial lattice strain, a second semiconductor layer covering both sides of the buried insulating film and both sides of the first semiconductor layer, the sides being opposite in the gate-length direction, a gate electrode formed on the first semiconductor layer with a gate insulating film being formed between the gate electrode and the first semiconductor, and a source region and a drain region which are formed in the second semiconductor layer.
摘要翻译：包括MIS晶体管的半导体器件。该器件包括形成在衬底的一部分中的掩埋绝缘膜，所述埋入绝缘膜在栅极宽度方向上伸长并在MIS晶体管的栅极长度方向上缩短，形成在掩埋绝缘膜上的第一半导体层并且具有单轴晶格应变，覆盖所述埋入绝缘膜的两侧以及所述第一半导体层的两侧在所述栅极长度方向上相反的两侧的第二半导体层，在所述第一半导体层上形成有栅极的栅电极在栅电极和第一半导体之间形成的绝缘膜，以及形成在第二半导体层中的源极区和漏极区。

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