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    • 6. 发明授权
    • Subirrigation system
    • 子灌溉系统
    • US09011041B2
    • 2015-04-21
    • US12675531
    • 2008-08-25
    • Naoki OnoHiroaki SakamotoKazuhiro HiraoToshinobu KakitaYasushi WadaYoshihito FujiiTsuneo Onodera
    • Naoki OnoHiroaki SakamotoKazuhiro HiraoToshinobu KakitaYasushi WadaYoshihito FujiiTsuneo Onodera
    • E02B11/00A01G25/06
    • A01G25/06
    • A subirrigation system 10 includes a water-impervious member 16, and keeps water content in soil of a cultivated land 200 in a proper state for growing a plant. The water-impervious member 16 is formed into an upper opening vessel shape, and has a water reserving function. Water is fed to an inner portion of the water-impervious member 16 from a water tank 12 via a feed water pipe 14, whereby a soil portion 26 in a gravitational water state is formed. A water level 28 of the gravitational water within the water-impervious member 16 is properly controlled to a desired water level by a water level controller 18 provided in the feed water pipe 14. The gravitational water within the water-impervious member 16 controlled to the desired water level is appropriately sucked up to the soil in an upper layer in accordance with a capillary phenomenon. Accordingly, a soil portion 30 in a capillary water state having proper water content is formed in the cultivated land 200.
    • 子灌溉系统10包括不透水构件16,并且在适当的状态下将耕地200的土壤中的含水量保持在植物生长中。 防水构件16形成为上开口容器形状,并具有储水功能。 水通过给水管14从水箱12供给到不透水构件16的内部,由此形成重力水状态的土壤部分26。 不透水构件16内的重力水的水位28被设置在给水管14中的水位控制器18适当地控制到期望的水位。防水构件16内的重力控制到 根据毛细管现象,期望的水位被适当吸入上层的土壤。 因此,在耕地200中形成具有适当含水量的毛细水分状态的土壤部分30。
    • 7. 发明授权
    • Multiplier, and fixed coefficient FIR digital filter having plural multipliers
    • 具有多个乘法器的乘法器和固定系数FIR数字滤波器
    • US06311203B1
    • 2001-10-30
    • US09203373
    • 1998-12-02
    • Yasushi WadaShuji Murakami
    • Yasushi WadaShuji Murakami
    • G06F752
    • H03H17/06G06F7/523
    • A multiplication device for performing a multiplication operation on a multiplicand X and two fixed coefficients C1 and C2 where C1>C2. The multiplication device comprises a multiplier for multiplying multiplicand X and the average CA of the two fixed coefficients C1 and C2; a shift register for obtaining a sum of the multiplicand X data after being shifted up according to a position of a “1” bit in bit data where the bit data is the remainder coefficient obtained by subtracting average CA from fixed coefficient C1; and a selector for selecting a product obtained for one of the fixed coefficients C1 and C2. When the fixed coefficient C1 is selected, the selector outputs the sum of the product returned by the multiplier and the accumulated value obtained by the shift register; when fixed coefficient C2 is selected, the selector outputs the difference of the product returned by the multiplier minus the accumulated value obtained by the shift register. A fixed coefficient FIR digital filter having a plurality of multiplication devices above-mentioned is also disclosed.
    • 用于对被乘数X和两个固定系数C1和C2执行乘法运算的乘法装置,其中C1> C2。 乘法装置包括用于将被乘数X与两个固定系数C1和C2的平均CA相乘的乘法器; 移位寄存器,用于根据比特数据中的“1”位的位置向上移位被乘数X数据,其中比特数据是通过从固定系数C1减去平均CA而获得的余数系数; 以及选择器,用于选择为固定系数C1和C2之一获得的乘积。 当选择固定系数C1时,选择器输出由乘法器返回的乘积和由移位寄存器获得的累加值之和; 当选择固定系数C2时,选择器输出由乘数返回的乘积的差值减去由移位寄存器获得的累加值。 还公开了具有上述多个乘法装置的固定系数FIR数字滤波器。
    • 9. 发明授权
    • Logic optimization device for automatically designing integrated circuits
    • 用于自动设计集成电路的逻辑优化装置
    • US06834376B2
    • 2004-12-21
    • US10212768
    • 2002-08-07
    • Yasushi Wada
    • Yasushi Wada
    • G06F1750
    • G06F17/505
    • A logic optimization device refers to hierarchical circuit-design descriptions representing multiple layers of an integrated circuit, and decides whether or not each output terminal at each lower layer is connected with its upper layer. If an output terminal at a lower layer has been decided to be unconnected with its upper layer, the logic optimization device deletes from the hierarchical circuit-design descriptions an information part describing the output terminal, and deletes from the hierarchical circuit-design descriptions an information part describing an element at the lower layer connected with the deleted output terminal, thereby producing a gate-level net-list of an integrated circuit without ineffectual elements.
    • 逻辑优化装置是指表示集成电路的多层的分层电路设计描述,并且判定每个下层的每个输出端是否与其上层连接。 如果下层的输出端子决定与其上层不连接,则逻辑优化装置从分层电路设计描述中删除描述输出端子的信息部分,并从分层电路设计描述中删除信息 描述与删除的输出端子连接的下层的元件的部分,由此产生集成电路的门级网络列表,而没有无效元件。
    • 10. 发明授权
    • Formal logic verification system and method
    • 正式逻辑验证系统及方法
    • US06453449B1
    • 2002-09-17
    • US09360641
    • 1999-07-26
    • Yasushi Wada
    • Yasushi Wada
    • G06F1750
    • G06F17/504
    • There is described a means of shortening of the time required for verification by a formal logic verification system which compares details of a circuit represented in the form of a register transfer level (RTL) description with details of the circuit represented in the form of a gate level netlist. Logical equivalence between an RTL description and a gate level netlist obtained through logical compilation of the RTL descriptions is verified. In a case where a plurality of blocks having the same function are included in the circuit, one of a plurality of descriptions that are included in the netlist and relate to the function is compared with the RTL description relating to the functional blocks (comparison {circle around (1)}). If one of the descriptions of the netlist has already been verified, a plurality of descriptions included in the netlist are compared with the description that is taken as the first reference description.
    • 描述了通过形式逻辑验证系统来缩短验证所需的时间的手段,该系统比较以寄存器传送级(RTL)描述形式表示的电路的细节与以门的形式表示的电路的细节 级别网表。 验证通过RTL描述的逻辑编译获得的RTL描述和门级网表之间的逻辑等价性。 在具有相同功能的多个块包括在电路中的情况下,将包括在网表中并涉及功能的多个描述之一与与功能块相关的RTL描述进行比较(比较{circle around(1)})。 如果网表的描述之一已经被验证,则将包括在网表中的多个描述与作为第一参考描述的描述进行比较。