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1. 发明申请

US20070235708A1 Programmable via structure for three dimensional integration technology 有权
标题翻译：可编程通孔结构，用于三维集成技术
公开(公告)号：US20070235708A1
公开(公告)日：2007-10-11
申请号：US11393270
申请日：2006-03-30
申请人： Bruce Elmegreen , Lia Krusin-Elbaum , Chung Lam , Dennis Newns , Matthew Wordeman , Albert Young
发明人： Bruce Elmegreen , Lia Krusin-Elbaum , Chung Lam , Dennis Newns , Matthew Wordeman , Albert Young
IPC分类号： H01L29/04
CPC分类号： H01L45/144 , H01L23/5226 , H01L23/5252 , H01L23/5256 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/1286 , H01L2924/0002 , H01L2924/00
摘要： A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof.
摘要翻译：用于三维积分（3DI）半导体器件的可编程链路结构包括至少部分地填充有相变材料（PCM）和靠近PCM的加热装置的通孔。加热装置被配置为将PCM的可变形部分的电导率切换到较低电阻结晶状态和较高电阻无定形状态。因此，通路限定位于其一端的输入连接与位于其另一端的输出连接之间的可编程连接。

2. 发明申请

US20050045872A1 Gradiometer-based flux qubit for quantum computing and method therefor 失效
标题翻译：用于量子计算的基于Gradiometer的通量量子位及其方法
公开(公告)号：US20050045872A1
公开(公告)日：2005-03-03
申请号：US10648346
申请日：2003-08-27
申请人： Dennis Newns , David DiVincenzo , Roger Koch , Glenn Martyna , Jim Rozen , Chang Tsuei
发明人： Dennis Newns , David DiVincenzo , Roger Koch , Glenn Martyna , Jim Rozen , Chang Tsuei
IPC分类号： G06N99/00 , H01L29/06
CPC分类号： G06N99/002 , B82Y10/00 , Y10S977/933
摘要： A qubit (quantum bit) circuit includes a superconducting main loop that is electrically-completed by a serially-interconnected superconducting subloop. The subloop includes two Josephson junctions. A first coil provides a first flux that couples with the main loop but not with the subloop. A second coil provides a second flux that couples with the subloop but not with the main loop.
摘要翻译：量子位（量子比特）电路包括通过串联互连超导子环电气完成的超导主环路。亚循环包括两个约瑟夫逊路口。第一线圈提供与主环路耦合但不与子环路耦合的第一通量。第二线圈提供与次环耦合但不与主回路耦合的第二通量。

3. 发明申请

US20070145347A1 Coupled quantum well devices (CQWD) containing two or more direct selective contacts and methods of making same 失效
标题翻译：包含两个或更多个直接选择性接触的耦合量子阱器件（CQWD）及其制造方法
公开(公告)号：US20070145347A1
公开(公告)日：2007-06-28
申请号：US11315691
申请日：2005-12-22
申请人： Yasunao Katayama , Dennis Newns , Chang Tsuei
发明人： Yasunao Katayama , Dennis Newns , Chang Tsuei
IPC分类号： H01L29/06
CPC分类号： H01L29/152 , B82Y10/00 , G11C11/14 , H01L29/41766 , H01L29/66431 , H01L29/66462 , H01L29/7782 , H01L29/7783 , Y10S977/937
摘要： The present invention relates to a device structure that contains two or more conducting layers, two peripheral insulating layers, one or more intermediate insulating layers, and two or more conductive contacts. The two or more conducting layers are sandwiched between the two peripheral insulating layers, and they are spaced apart by the intermediate insulating layers to form two or more quantum wells. Each of the conductive contacts is directly and selectively connected with one of the conducting layers, so the individual quantum wells can be selectively accessed through the conductive contacts. Such a device structure preferably contains a coupled quantum well devices having two or more quantum wells that can be coupled together by inter-well tunneling effect at degenerate energy levels. More preferably, the device structure contains a memory cell having three quantum wells that can be arranged and constructed to define two different memory states.
摘要翻译：本发明涉及一种器件结构，其包含两个或多个导电层，两个外围绝缘层，一个或多个中间绝缘层以及两个或多个导电触点。两个或更多个导电层夹在两个外围绝缘层之间，并且它们被中间绝缘层隔开以形成两个或更多个量子阱。每个导电触点直接和选择性地连接到导电层中的一个，因此可以通过导电触点选择性地访问各个量子阱。这样的器件结构优选地包含具有两个或更多个量子阱的耦合量子阱器件，所述量子阱可以在简并能级处通过阱间隧道效应耦合在一起。更优选地，器件结构包含具有三个量子阱的存储单元，其可以被布置和构造以限定两个不同的存储器状态。

4. 发明申请

US20060249724A1 Method and structure for Peltier-controlled phase change memory 审中-公开
标题翻译：珀耳帖控制相变记忆的方法和结构
公开(公告)号：US20060249724A1
公开(公告)日：2006-11-09
申请号：US11123086
申请日：2005-05-06
申请人： Lia Krusin-Elbaum , Dennis Newns
发明人： Lia Krusin-Elbaum , Dennis Newns
IPC分类号： H01L29/02
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1206 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/144 , H01L45/148
摘要： A memory cell includes a phase change material (PCM) element that stores an information bit. A heating element external to the PCM element changes the information bit. A cooling element increases the speed of the information bit change.
摘要翻译：存储单元包括存储信息位的相变材料（PCM）元件。 PCM元件外部的加热元件会更改信息位。冷却元件增加了信息位变化的速度。

5. 发明申请

US20050095389A1 Method and structure for ultra-high density, high data rate ferroelectric storage disk technology using stabilization by a surface conducting layer 失效
标题翻译：采用表面导电层稳定化的超高密度，高数据速率的铁电存储盘技术的方法和结构
公开(公告)号：US20050095389A1
公开(公告)日：2005-05-05
申请号：US10697271
申请日：2003-10-31
申请人： Dennis Newns
发明人： Dennis Newns
IPC分类号： B32B3/02
CPC分类号： G11C11/22 , G11B9/02 , G11B9/063 , Y10T428/11 , Y10T428/1171
摘要： A method and structure for a ferroelectric storage medium, includes a metallic underlayer and a ferroelectric data layer over the metallic underlayer. A layer over the ferroelectric data layer has a charge migration rate faster than a charge migration rate of the ferroelectric data layer.
摘要翻译：铁电存储介质的方法和结构包括在金属底层上的金属底层和铁电数据层。铁电数据层上的层的电荷迁移速率比铁电数据层的电荷迁移速率快。

6. 发明申请

US20070235784A1 Three-terminal cascade switch for controlling static power consumption in integrated circuits 失效
标题翻译：用于控制集成电路静态功耗的三端子级联开关
公开(公告)号：US20070235784A1
公开(公告)日：2007-10-11
申请号：US11393259
申请日：2006-03-30
申请人： Lia Krusin-Elbaum , Dennis Newns , Matthew Wordeman
发明人： Lia Krusin-Elbaum , Dennis Newns , Matthew Wordeman
IPC分类号： H01L29/94
CPC分类号： H01L45/1226 , H01L27/24 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/1286 , H01L45/144 , H01L45/148
摘要： A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.
摘要翻译：配置成用于控制集成电路中的静态功耗的开关电路包括连接在电压源端子和集成电路逻辑的对应子块之间的多个三端子相变材料（PCM）开关器件。每个PCM开关装置还包括设置在第一端子和第二端子之间接触的PCM，在第二端子和第三端子之间接触地设置的加热装置，加热装置位于PCM附近，并且被配置为将 PCM的可变形部分的电导率在较低电阻结晶状态和较高电阻无定形状态之间; 以及绝缘层，其被配置为将加热器与所述PCM材料电隔离，并且所述加热器与所述第一端子电隔离。第一个PCM开关器件的第三个端子耦合到一个设置/复位开关，其余的PCM开关器件的第三个端子以级联配置耦合到相邻PCM开关器件的第二个端子。

7. 发明申请

US20060279978A1 Method and structure for high performance phase change memory 有权
标题翻译：高性能相变存储器的方法和结构
公开(公告)号：US20060279978A1
公开(公告)日：2006-12-14
申请号：US11150188
申请日：2005-06-13
申请人： Lia Krusin-Elbaum , Rudolf Ludeke , Dennis Newns , Simone Raoux
发明人： Lia Krusin-Elbaum , Rudolf Ludeke , Dennis Newns , Simone Raoux
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/003 , G11C2013/008 , G11C2213/72 , G11C2213/74 , G11C2213/79 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/144
摘要： A method (and structure) for a memory cell having a phase change material (PCM) element and a heating element external to the PCM element. The heating element causes one of a presence of and an absence of a phase boundary within the PCM element for storing information in the PCM element.
摘要翻译：一种用于具有PCM元件外部的相变材料（PCM）元件和加热元件的存储单元的方法（和结构）。加热元件在PCM元件中存在和不存在相位边界之一以将信息存储在PCM元件中。

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