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1. 发明授权

US4729022A Multiplexing system 失效
标题翻译：复用系统
公开(公告)号：US4729022A
公开(公告)日：1988-03-01
申请号：US701204
申请日：1985-02-13
申请人： Toru Shibuya , Mitsuo Nishiwaki
发明人： Toru Shibuya , Mitsuo Nishiwaki
IPC分类号： H04J3/04 , H04J3/16 , H04N1/00 , H04N7/08 , H04N7/04
CPC分类号： H04N1/001 , H04J3/1682
摘要： In a multiplexing system wherein data from a plurality of terminal units are multiplexed in time slots shared to the terminal units and coded picture data are multiplexed at least in time slots shared for picture, there are provided picture signal encoding means operating at a clock frequency independent of a clock frequency for a transmission path, a buffer memory circuit for storing the coded picture data outputted from the picture signal encoding means, a data detecting circuit for detecting presence or absence of output data from the plurality of terminal units and a multiplexing circuit which shares coded picture data read out from the buffer memory circuit to a time slot or time slots of terminal units whose output data are not detected by the data detecting circuit and which shares, to time slots of terminal unit whose output data are detected by the data detecting circuit, output data of these terminal units, thereby adaptively sharing coded picture data to the time slots for the terminal units.
摘要翻译：在多路复用系统中，其中来自多个终端单元的数据在与终端单元共用的时隙中多路复用，而编码图像数据至少在与图像共享的时隙中多路复用，提供了以时钟频率独立运行的图像信号编码装置用于传输路径的时钟频率，用于存储从图像信号编码装置输出的编码图像数据的缓冲存储器电路，用于检测来自多个终端单元的输出数据的存在或不存在的数据检测电路，以及复用电路，将从缓冲存储器电路读出的编码图像数据共享到其数据检测电路未检测到输出数据的终端单元的时隙或时隙，并且共享到其数据被数据检测到的输出数据的终端单元的时隙检测电路，这些终端单元的输出数据，从而将经编码的图像数据自适应地分配到t的时隙他的终端单位。

2. 发明授权

US4807028A Decoding device capable of producing a decoded video signal with a reduced delay 失效
标题翻译：解码装置能够以减小的延迟产生解码的视频信号
公开(公告)号：US4807028A
公开(公告)日：1989-02-21
申请号：US118922
申请日：1987-11-10
申请人： Yoshinori Hatori , Mitsuo Nishiwaki , Naoki Mukawa
发明人： Yoshinori Hatori , Mitsuo Nishiwaki , Naoki Mukawa
IPC分类号： H04N19/102 , H04N7/60 , H04N19/00 , H04N19/134 , H04N19/15 , H04N19/172 , H04N19/196 , H04N19/423 , H04N19/44 , H04N19/46 , H04N19/70 , H04N7/137
CPC分类号： H04N21/434 , H04N19/00 , H04N19/587 , H04N19/59 , H04N21/236
摘要： For decoding by the use of a decoder buffer memory an encoded video signal into which an encoder input signal is encoded with data compression on a basis of frames, a decoding device comprises a control signal producing unit for delivering a decoder control signal to a decoder when the frame of data written into the buffer memory coincides with the frame of data read out of the buffer memory. Responsive to the control signal, the decoder produces a supply control signal to the buffer memory to stop delivery of the read-out data to the decoder. Preferably, the decoding device should comprise a processing unit for producing frame pulses at heads of the respective frames of the encoded video signal. A counter counts the frame head pulses to make the write-in data and the read-out data indicate frame numbers for use in the signal producing unit. Alternatively, the decoding device may receive an encoded video signal in which frame number data are included for use in the signal producing unit.
摘要翻译：为了通过使用解码器缓冲存储器对基于帧进行数据压缩对编码器输入信号进行编码的编码视频信号进行解码，解码装置包括控制信号产生单元，用于将译码器控制信号传送到解码器，写入缓冲存储器的数据帧与从缓冲存储器读出的数据帧一致。响应于控制信号，解码器向缓冲存储器产生供应控制信号，以停止向解码器传送读出的数据。优选地，解码装置应包括用于在编码视频信号的各个帧的头部处产生帧脉冲的处理单元。计数器对帧头脉冲进行计数以使写入数据和读出数据指示用于信号产生单元的帧号。或者，解码装置可以接收编码的视频信号，其中包括帧号数据以供在信号产生单元中使用。

3. 发明授权

US4679081A System for coding video signal in block unit 失效
标题翻译：用于以块为单位对视频信号进行编码的系统
公开(公告)号：US4679081A
公开(公告)日：1987-07-07
申请号：US796690
申请日：1985-11-12
申请人： Syuzo Tsugane , Mitsuo Nishiwaki
发明人： Syuzo Tsugane , Mitsuo Nishiwaki
IPC分类号： H01L21/8246 , B82Y10/00 , B82Y25/00 , G11B5/39 , H01F10/30 , H01L27/105 , H01L43/08 , H01L43/10 , H04N1/415 , H04N7/62 , H04N19/00 , H04N19/50 , H04N1/40 , H04N7/12
CPC分类号： H04N19/593
摘要： A system for coding video signals e.g. television signals in block units is disclosed. The coding system comprises a synchronization detector for detecting a frame synchronization from the video signal, and a block former operative to divide the video signal in block units per a predetermined number of lines by using a picture frame synchronization signal detected by the synchronization detector as a reference. When the number of lines included in a block immediately before the subsequent picture frame synchronization signal is less than the predetermined number of lines, the block former designates the block as an ineffective block. The coding system further comprises a coder operative to apply a coding processing to the blocks except for the ineffective block designated by the block former in accordnace with a predetermined coding procedure, and transmitter operative to multiplex coded data outputted from the block former and coder, position information of the first block immediately after the picture frame synchronization signal, and the number of lines within the ineffective block so as to transmit the multiplexed signal thus obtained. Thus, when the input video signal is asynchronously switched, the coding system necessarily executes only a processing per each block, thus providing a reproduced picture image free from distortion on the side of a receiving station.
摘要翻译：一种用于对视频信号进行编码的系统。公开了以块为单位的电视信号。该编码系统包括用于从视频信号中检测帧同步的同步检测器，以及块形成器，其可以通过使用由同步检测器检测的图像帧同步信号作为预定数量的线以块为单位划分视频信号，作为参考。当包含在紧接在后面的图像帧同步信号之前的块中的行数小于预定行数时，块形成器将该块指定为无效块。该编码系统进一步包括一个编码器，用于根据预定的编码过程，将编码处理应用于块编码器指定的无效块以外的块，以及发送器，用于对从块编码器和编码器输出的编码数据进行多路复用紧接在图像帧同步信号之后的第一块的信息和无效块内的行数，以便发送由此获得的多路复用信号。因此，当输入视频信号被异步切换时，编码系统必须仅执行每个块的处理，从而提供在接收站侧没有失真的再现图像图像。

4. 发明授权

US4688233A Digital data transmitting device for communication paths of restricted and unrestricted transmission characteristics 失效
标题翻译：数字数据发送装置，用于限制和不受限制的传输特性的通信路径
公开(公告)号：US4688233A
公开(公告)日：1987-08-18
申请号：US796094
申请日：1985-11-07
申请人： Mitsuo Nishiwaki , Tooru Amano , Tooru Yasuda , Sakae Okubo , Naoki Mukawa
发明人： Mitsuo Nishiwaki , Tooru Amano , Tooru Yasuda , Sakae Okubo , Naoki Mukawa
IPC分类号： H04J3/07 , H04L7/00
CPC分类号： H04J3/073
摘要： In a digital data communication network comprising digital data transmitting and receiving devices (111, 122) and first and second digital communication paths (16, 17) connected to each other and to the transmitting and the receiving devices, respectively, a stuffing circuit (23) is controlled by a control signal producing circuit (24) so as to stuff and not to stuff an input bit sequence when at least one of the first and the second digital communication paths has a restricted transmission characteristic and when both of the communication paths have an unrestricted transmission characteristic. Preferably, necessity and unnecessity of stuffing should be detected for a leading and a trailing part of each block with a shorter interval of time than for other parts of the block. More preferably, some of binary one bits placed at the beginnings of the respective blocks are used as a part of a multiframe synchronization pattern for a signal transmitted through the communication paths.
摘要翻译：在包括数字数据发送和接收装置（111,122）以及分别连接到发送和接收装置的第一和第二数字通信路径（16,17）的数字数据通信网络中，分别包括填充电路）由控制信号产生电路（24）控制，以便当第一和第二数字通信路径中的至少一个具有受限的传输特性时，填充和不填充输入比特序列，并且当两个通信路径具有无限制的传输特性。优选地，对于每个块的前导部分和尾部部分，对于块的其他部分，间隔时间较短，应该检测填充的必要性和不必要性。更优选地，放置在相应块的开始处的二进制一位中的一些被用作通过通信路径传输的信号的多帧同步模式的一部分。

5. 发明授权

US4353129A Digital data transmission system 失效
标题翻译：数字数据传输系统
公开(公告)号：US4353129A
公开(公告)日：1982-10-05
申请号：US240940
申请日：1981-03-05
申请人： Mitsuo Nishiwaki
发明人： Mitsuo Nishiwaki
IPC分类号： H04B14/04 , H04J3/07 , H04L7/00 , H04L7/04 , H04L7/08 , H04L25/49
CPC分类号： H04J3/07 , H04L25/4915 , H04L2007/045
摘要： A digital data transmission system comprises a transmitter and a receiver, said transmitter comprising storage means for temporarily storing a data bit string forming a coded digital video signal, means for supplying a read request signal for reading out said data bit string from said storage means, means for forming one frame out of time slots alloted to a frame synchronization bit, a predetermined number of data bit of said data bit string and a dummy flag bit which indicates whether or not a dummy bit exists in said one frame, means for detecting whether or not a fixed bit pattern is formed in said one frame, means for providing said dummy bit to a predetermined one of said time slots in response to the result of said detection, means for inserting a dummy flag bit indicative of whether or not the dummy bit has been inserted to a time slot for said dummy flag bit, means for supplying a data bit which have dropped out by addition of said dummy bit to said frame forming means so that said dropped data bit is inserted as a part of said data bits forming a succeeding frame, and means for suspending the supply of said read request signal for the bit corresponding to said dropped data bit; said receiver comprising an input terminal for receiving in serial fashion the transmitted data bit string supplied from said transmitter, means for detecting said dummy flag bit in said transmitted data bit string, and means for separating said transmitted data bit string into a dummy bit and input data bits in response to the detection of said dummy flag bit.
摘要翻译：数字数据传输系统包括发射机和接收机，所述发射机包括用于临时存储形成编码数字视频信号的数据比特串的存储装置，用于提供从所述存储装置读出所述数据比特串的读请求信号的装置，用于在分配给帧同步位的时隙中形成一帧的装置，所述数据位串的预定数量的数据位和指示在所述一帧中是否存在虚拟位的伪标志位的装置，用于检测是否或者在所述一帧中不形成固定位模式，用于响应于所述检测结果将所述虚拟位提供给所述时隙中的预定的一个的装置，用于插入虚拟标志位的装置，位被插入到用于所述伪标志位的时隙中，用于将通过添加所述伪位而丢弃的数据位提供给所述帧形成装置的装置，使得所述丢弃数据位被插入作为形成后续帧的所述数据位的一部分，以及用于暂停对与所述丢弃数据位相对应的位的所述读取请求信号的提供的装置; 所述接收机包括用于以串行方式接收从所述发射机提供的发射数据比特串的输入端，用于检测所述发送数据比特串中的所述伪标志位的装置，以及用于将所述发送的数据比特串分成虚拟比特和输入的装置数据位响应于所述伪标志位的检测。

6. 发明授权

US4791485A System for detecting a transmission error 失效
标题翻译：用于检测传输错误的系统
公开(公告)号：US4791485A
公开(公告)日：1988-12-13
申请号：US929435
申请日：1986-12-19
申请人： Hideo Kuroda , Naoki Mukawa , Makoto Hiraoka , Kiichi Matsuda , Mitsuo Nishiwaki , Shuzo Tsugane
发明人： Hideo Kuroda , Naoki Mukawa , Makoto Hiraoka , Kiichi Matsuda , Mitsuo Nishiwaki , Shuzo Tsugane
IPC分类号： H03M13/00 , H04B14/06 , H04L1/00 , H04N19/50 , H04N7/12
CPC分类号： H04N19/895 , H04N19/50
摘要： An inter-frame encoding/decoding equipment for television signals consists of inter-frame encoding equipment encoding a difference between television signals and the output of a frame memory and inter-frame decoding equipment which receives an encoded signal sent from the inter-frame encoding device via a transmission line, which decodes by adding the output of the frame memory to the encoded signal. The inter-frame encoding equipment is provided with a first operation circuit which operates the remainders obtained by dividing, by a predetermined value, the number of bits of logic "1" in the bit groups into which the output or the input of the frame memory is divided by a predetermined unit. The inter-frame decoding equipment is provided with a second operation circuit which operates the remainders obtained by dividing, by a predetermined value, the number of bits of logic "1" in the bit groups into which the output or the input of the frame memory is divided by a predetermined unit. The inter-frame decoding equipment is further provided with a comparator circuit which compares and checks the values operated by the first and the second operation circuits to detect a transmission error.

7. 发明授权

US4731664A Method and arrangement for refreshing a frame memory in an interframe encoding system 失效
标题翻译：在帧间编码系统中刷新帧存储器的方法和装置
公开(公告)号：US4731664A
公开(公告)日：1988-03-15
申请号：US794667
申请日：1985-11-04
申请人： Mitsuo Nishiwaki , Shuzo Tsugane , Naoki Mukawa , Hideo Kuroda
发明人： Mitsuo Nishiwaki , Shuzo Tsugane , Naoki Mukawa , Hideo Kuroda
IPC分类号： G06F12/00 , H04N7/60 , H04N19/50 , H04N21/236 , H04N21/434 , H04N7/12 , H04N7/04
CPC分类号： H04N21/434 , H04N19/152 , H04N19/503 , H04N19/61 , H04N21/236 , H04N19/107 , H04N19/50
摘要： A video signal frame memory is refreshed without requiring either a separate transmission line or the transmission of bursts of data. This is done by dividing the frame signals into blocks of data, which are further divided into lines and sub-blocks. During each frame, refreshing signals are sent on a sub-block basis, thereby distributing the refreshing control signals and preventing many signals from being sent in bursts.
摘要翻译：视频信号帧存储器被刷新，而不需要单独的传输线或数据的突发的传输。这通过将帧信号划分成数据块来完成，数据块被进一步划分成行和子块。在每个帧期间，以子块为基础发送刷新信号，由此分配刷新控制信号并防止许多信号以突发方式发送。

8. 发明授权

US4677480A System for detecting a transmission error 失效
标题翻译：用于检测传输错误的系统
公开(公告)号：US4677480A
公开(公告)日：1987-06-30
申请号：US620516
申请日：1984-06-14
申请人： Hideo Kuroda , Naoki Mukawa , Makoto Hiraoka , Kiichi Matsuda , Mitsuo Nishiwaki , Shuzo Tsugane
发明人： Hideo Kuroda , Naoki Mukawa , Makoto Hiraoka , Kiichi Matsuda , Mitsuo Nishiwaki , Shuzo Tsugane
IPC分类号： H03M13/00 , H04B14/06 , H04L1/00 , H04N19/50 , H04N7/12
CPC分类号： H04N19/895 , H04N19/50
摘要： Inter-frame encoding/decoding equipment for television signals includes inter-frame encoding equipment generating an encoded signal by encoding a difference between television signals and the output of a frame memory and inter-frame decoding equipment which receives the encoded signal sent from the inter-frame encoding device via a transmission line. The decoding equipment decodes by adding its output of the frame memory to the encoded signal. The inter-frame encoding equipment is provided with a first operation circuit which calculates remainders obtained by dividing a predetermined value, into bit groups of the output or the input of the frame memory. The inter-frame decoding equipment is provided with a second operation circuit which calculates remainders obtained by dividing, the predetermined value, into the bit groups of the output or the input of its frame memory. The inter-frame decoding equipment is further provided with a comparator circuit which compares and checks the remainders calculated by the first and the second operation circuits to detect a transmission error.
摘要翻译：用于电视信号的帧间编码/解码设备包括帧间编码设备，通过编码电视信号与帧存储器的输出之间的差异以及帧间解码设备产生编码信号，帧间解码设备接收从帧间编码信号发送的编码信号，帧编码装置。解码设备通过将帧存储器的输出加到编码信号来进行解码。帧间编码装置设置有第一运算电路，其计算通过将预定值除以获得的余数到帧存储器的输出或输入的比特组。帧间解码装置设置有第二运算电路，其计算通过将预定值除以其帧存储器的输出或输入的位组而获得的余数。帧间解码装置还具备比较电路，比较电路，对由第一和第二运算电路计算出的余数进行比较和检查，以检测传输误差。

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