专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08309414B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08309414B2
公开(公告)日：2012-11-13
申请号：US12805291
申请日：2010-07-22
申请人： Toru Kawasaki , Satoshi Kura , Mitsuo Nissa , Naotaka Kamishita
发明人： Toru Kawasaki , Satoshi Kura , Mitsuo Nissa , Naotaka Kamishita
IPC分类号： H01L27/088 , H01L21/8239
CPC分类号： H01L27/10894 , H01L21/823468 , H01L27/088 , H01L27/10873 , H01L29/6653
摘要： A first transistor includes a first gate insulating film, a first gate electrode, and a first sidewall. A second transistor includes a second gate insulating film, a second gate electrode, and a second sidewall. A capacitive element is connected to one side of source and drain regions of the second transistor. The first gate insulating film has the same thickness as that of the second gate insulating film, and the first gate electrode has the same thickness of that of the second gate electrode. The width of the second sidewall is larger than the width of the first sidewall.
摘要翻译：第一晶体管包括第一栅极绝缘膜，第一栅电极和第一侧壁。第二晶体管包括第二栅极绝缘膜，第二栅电极和第二侧壁。电容元件连接到第二晶体管的源区和漏区的一侧。第一栅极绝缘膜具有与第二栅极绝缘膜相同的厚度，并且第一栅极电极具有与第二栅极电极的厚度相同的厚度。第二侧壁的宽度大于第一侧壁的宽度。

2. 发明申请

US20110042749A1 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20110042749A1
公开(公告)日：2011-02-24
申请号：US12805291
申请日：2010-07-22
申请人： Toru Kawasaki , Satoshi Kura , Mitsuo Nissa , Naotaka Kamishita
发明人： Toru Kawasaki , Satoshi Kura , Mitsuo Nissa , Naotaka Kamishita
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/10894 , H01L21/823468 , H01L27/088 , H01L27/10873 , H01L29/6653
摘要： A first transistor includes a first gate insulating film, a first gate electrode, and a first sidewall. A second transistor includes a second gate insulating film, a second gate electrode, and a second sidewall. A capacitive element is connected to one side of source and drain regions of the second transistor. The first gate insulating film has the same thickness as that of the second gate insulating film, and the first gate electrode has the same thickness of that of the second gate electrode. The width of the second sidewall is larger than the width of the first sidewall.
摘要翻译：第一晶体管包括第一栅极绝缘膜，第一栅电极和第一侧壁。第二晶体管包括第二栅极绝缘膜，第二栅电极和第二侧壁。电容元件连接到第二晶体管的源区和漏区的一侧。第一栅极绝缘膜具有与第二栅极绝缘膜相同的厚度，并且第一栅极电极具有与第二栅极电极的厚度相同的厚度。第二侧壁的宽度大于第一侧壁的宽度。

3. 发明授权

US06674137B2 Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06674137B2
公开(公告)日：2004-01-06
申请号：US09997593
申请日：2001-11-29
申请人： Mitsuo Nissa
发明人： Mitsuo Nissa
IPC分类号： H01L27108
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/823425 , H01L21/823456
摘要： A semiconductor device is disclosed that can include a gate electrode (6) having a lower layer (6a) and a higher layer (6b), a mask insulating film (7) formed over a higher layer (6b). A side surface insulating film (9) may be formed on sides of a gate electrode (6) and a side wall insulating film (8) may be formed on the sides of a gate electrode (6) and mask insulating film (7). A low density impurity region (3) may be formed with a gate electrode (6) and side surface insulating film (9) as a mask. A higher density impurity region (4) may be formed with a gate electrode (6) and side wall insulating film (8) as a mask. A contact plug (10) may be formed between side wall insulating films (8) that contacts a higher density impurity region (4). A gate electrode (6) may have a reverse tapered shape when viewed in cross section. A lower layer (6a) may have a reverse tapered shape and/or a side surface insulating film (9) may have a greater thickness on sides of a higher layer (6b) than on a lower layer (6a).
摘要翻译：公开了一种半导体器件，其可以包括具有下层（6a）和更高层（6b）的栅电极（6），在较高层（6b）上形成的掩模绝缘膜（7）。可以在栅电极（6）的侧面上形成侧面绝缘膜（9），并且可以在栅电极（6）和掩模绝缘膜（7）的侧面上形成侧壁绝缘膜（8）。低浓度杂质区域（3）可以形成有栅电极（6）和侧面绝缘膜（9）作为掩模。可以用栅电极（6）和侧壁绝缘膜（8）作为掩模形成更高密度的杂质区域（4）。可以在接触较高密度杂质区域（4）的侧壁绝缘膜（8）之间形成接触插塞（10）。当在横截面中观察时，栅电极（6）可以具有倒锥形形状。下层（6a）可以具有倒锥形形状和/或侧表面绝缘膜（9）可以在较高层（6b）的侧面上比在下层（6a）上具有更大的厚度。

4. 发明授权

US07932153B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07932153B2
公开(公告)日：2011-04-26
申请号：US12605875
申请日：2009-10-26
申请人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
发明人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
IPC分类号： H01L21/8236
CPC分类号： H01L21/823456 , H01L21/823412 , H01L21/823462 , H01L27/10894
摘要： A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.
摘要翻译：在用于形成第一MIS晶体管的阈值控制层的相同条件下形成第二MIS晶体管的阈值控制层。在与形成第三晶体管的LDD区域相同的条件下形成第二MIS晶体管的LLD区域。

5. 发明授权

US07622777B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07622777B2
公开(公告)日：2009-11-24
申请号：US11544653
申请日：2006-10-10
申请人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
发明人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
IPC分类号： H01L27/088
CPC分类号： H01L21/823456 , H01L21/823412 , H01L21/823462 , H01L27/10894
摘要： A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.
摘要翻译：在用于形成第一MIS晶体管的阈值控制层的相同条件下形成第二MIS晶体管的阈值控制层。在与形成第三晶体管的LDD区域相同的条件下形成第二MIS晶体管的LLD区域。

6. 发明申请

US20100047983A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100047983A1
公开(公告)日：2010-02-25
申请号：US12605875
申请日：2009-10-26
申请人： Takashi NAKABAYASHI , Hideyuki Arai , Mitsuo Nissa
发明人： Takashi NAKABAYASHI , Hideyuki Arai , Mitsuo Nissa
IPC分类号： H01L21/8234
CPC分类号： H01L21/823456 , H01L21/823412 , H01L21/823462 , H01L27/10894
摘要： A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.
摘要翻译：在用于形成第一MIS晶体管的阈值控制层的相同条件下形成第二MIS晶体管的阈值控制层。在与形成第三晶体管的LDD区域相同的条件下形成第二MIS晶体管的LLD区域。

7. 发明申请

US20070138571A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070138571A1
公开(公告)日：2007-06-21
申请号：US11544653
申请日：2006-10-10
申请人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
发明人： Takashi Nakabayashi , Hideyuki Arai , Mitsuo Nissa
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L21/823456 , H01L21/823412 , H01L21/823462 , H01L27/10894
摘要： A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.
摘要翻译：在用于形成第一MIS晶体管的阈值控制层的相同条件下形成第二MIS晶体管的阈值控制层。在与形成第三晶体管的LDD区域相同的条件下形成第二MIS晶体管的LLD区域。

8. 发明申请

US20060211170A1 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20060211170A1
公开(公告)日：2006-09-21
申请号：US11376339
申请日：2006-03-16
申请人： Kiyonori Oyu , Koji Hamada , Yasuhiro Uchiyama , Mitsuo Nissa
发明人： Kiyonori Oyu , Koji Hamada , Yasuhiro Uchiyama , Mitsuo Nissa
IPC分类号： H01L21/00 , H01L23/06
CPC分类号： H01L29/32 , H01L24/73 , H01L27/10844 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/19041 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device includes an N-type semiconductor region formed in a semiconductor substrate; a p-type semiconductor region formed in a region deeper in the semiconductor substrate than the N-type semiconductor region; and a heavy metal capturing region formed in a portion of the p-type semiconductor region to capture heavy metal ions. The heavy metal capturing region may be a P-type region. It is preferable that the diffusion speed of the heavy metal ions is slower in the heavy metal capturing region than in the p-type semiconductor region.
摘要翻译：半导体器件包括形成在半导体衬底中的N型半导体区域; 形成在所述半导体衬底中比所述N型半导体区域更深的区域中的p型半导体区域; 以及形成在p型半导体区域的一部分中以捕获重金属离子的重金属捕获区域。重金属捕获区域可以是P型区域。重金属捕获区域中的重金属离子的扩散速度优选比p型半导体区域慢。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式