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1. 发明授权

US06323756B1 Data transmitter 有权
标题翻译：数据发送器
公开(公告)号：US06323756B1
公开(公告)日：2001-11-27
申请号：US09486868
申请日：2000-05-26
申请人： Takefumi Yoshikawa , Toru Iwata , Hiroyuki Yamauchi
发明人： Takefumi Yoshikawa , Toru Iwata , Hiroyuki Yamauchi
IPC分类号： H04M1104
CPC分类号： H03K19/017545 , H03K19/0013
摘要： The data transmission device 1a of the present invention includes a driver 10 for sending data, a receiver 20 for receiving the data sent from the driver 10, a transmission line path 30 for connecting between the driver 10 and the receiver 20, and a variable impedance element 40 having a controllably variable impedance. The variable impedance element 40 is connected to the transmission line path 30. The data transmission line device 1a can reduce power consumption and occurrence of skew.
摘要翻译：本发明的数据传输装置1a包括用于发送数据的驱动器10，用于接收从驱动器10发送的数据的接收器20，用于连接驱动器10和接收器20的传输线路径30和可变阻抗元件40具有可控制的可变阻抗。可变阻抗元件40连接到传输线路径30.数据传输线设备1a可以降低功耗并产生偏斜。

2. 发明授权

US06426985B1 Variable delay circuit and phase adjustment circuit 失效
标题翻译：可变延迟电路和相位调整电路
公开(公告)号：US06426985B1
公开(公告)日：2002-07-30
申请号：US09283888
申请日：1999-04-01
申请人： Toru Iwata , Hiroyuki Yamauchi
发明人： Toru Iwata , Hiroyuki Yamauchi
IPC分类号： H04L700
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0818
摘要： A variable delay circuit includes a plurality of delay circuits for delaying an input signal; and a selection circuit for selecting an output from one of the plurality of delay circuits in accordance with a selection signal. The plurality of delay circuits include a first delay circuit for delaying the input signal by a first delay time period and a second delay circuit for delaying the input signal by a second delay time period which is longer than the first delay time period. The difference between the first delay time period and the second delay time period is shorter than a minimum delay time period which is allowed to be set in the first delay circuit.
摘要翻译：可变延迟电路包括用于延迟输入信号的多个延迟电路; 以及选择电路，用于根据选择信号选择多个延迟电路之一的输出。多个延迟电路包括用于将输入信号延迟第一延迟时间段的第一延迟电路和用于将输入信号延迟比第一延迟时间段长的第二延迟时间段的第二延迟电路。第一延迟时间段和第二延迟时间段之间的差值比允许在第一延迟电路中设置的最小延迟时间段短。

3. 发明授权

US06208567B1 Semiconductor device capable of cutting off a leakage current in a defective array section 失效
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置
公开(公告)号：US06208567B1
公开(公告)日：2001-03-27
申请号：US09014775
申请日：1998-01-28
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C2900
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

4. 发明授权

US5999022A Signal transmission driver circuit, receiver circuit, and method thereof for transmitting and receiving information based on multiple periods and/or a delay function 失效
标题翻译：用于基于多个周期和/或延迟功能发送和接收信息的信号传输驱动电路，接收机电路及其方法
公开(公告)号：US5999022A
公开(公告)日：1999-12-07
申请号：US631914
申请日：1996-04-15
申请人： Toru Iwata , Hironori Akamatsu , Hisakazu Kotani , Hiroyuki Yamauchi , Akira Matsuzawa , Shoichiro Tada
发明人： Toru Iwata , Hironori Akamatsu , Hisakazu Kotani , Hiroyuki Yamauchi , Akira Matsuzawa , Shoichiro Tada
IPC分类号： H03K19/00 , H03K19/0185 , H03K3/00
CPC分类号： H03K19/01855 , H03K19/0016
摘要： A driver circuit which drives a signal line includes a first output section for outputting a reference voltage potential to the signal line during a first period and a second output section for outputting one of a first information voltage potential and a second information voltage potential in accordance with an input signal during a second period.
摘要翻译：驱动信号线的驱动器电路包括：第一输出部，用于在第一时段期间向信号线输出参考电压电位;以及第二输出部，用于输出第一信息电压电位和第二信息电压电位之一在第二时段期间的输入信号。

5. 发明授权

US5757702A Data holding circuit 失效
标题翻译：数据保持电路
公开(公告)号：US5757702A
公开(公告)日：1998-05-26
申请号：US739363
申请日：1996-10-29
申请人： Toru Iwata , Hironori Akamatsu , Hiroyuki Yamauchi
发明人： Toru Iwata , Hironori Akamatsu , Hiroyuki Yamauchi
IPC分类号： G11C11/412 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419 , G11C11/412
摘要： A memory cell includes a first inverter and a second inverter connected with each other through the output node of one of the inverters and the input node of the other inverter, and first and second transistors. Each of the transistors connected with a word line at its gate electrode is interposed between one of a bit line pair and each memory node. This data holding circuit includes an element for increasing a memory cell supply potential for driving the pair of inverters to be higher than a supply potential applied to peripheral circuits, or an element for decreasing a ground voltage for driving the pair of inverters to be lower than a ground voltage applied to the peripheral circuits.
摘要翻译：存储单元包括通过其中一个反相器的输出节点和另一个反相器的输入节点以及第一和第二晶体管彼此连接的第一反相器和第二反相器。在其栅电极处与字线连接的晶体管中的每一个插入在位线对和每个存储器节点之一之间。该数据保持电路包括用于将用于驱动该对反相器的存储单元电源电位增加到高于施加到外围电路的电源电位的元件，或者用于将用于驱动该对反相器的接地电压降低到低于施加到外围电路的接地电压。

6. 发明授权

US06246627B1 Semiconductor device capable of cutting off a leakage current in a defective array section and method thereof 有权
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置及其方法
公开(公告)号：US06246627B1
公开(公告)日：2001-06-12
申请号：US09397239
申请日：1999-09-16
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C514
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

7. 发明授权

US6145065A Memory access buffer and reordering apparatus using priorities 失效
标题翻译：使用优先级的存储器访问缓冲器和重新排序装置
公开(公告)号：US6145065A
公开(公告)日：2000-11-07
申请号：US67899
申请日：1998-04-29
申请人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
发明人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F13/1631
摘要： A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed. This reduces the number of precharges, shortens a standby period which is necessary for a precharge, and realizes accessing while reducing a wasteful use of time.
摘要翻译：目前的问题在于，当通过数据总线访问DRAM时，独立于存储体，行地址等访问DRAM，因此是低效的。为了解决这个问题，地址总线和数据总线彼此独立地连接到主存储器部分，预先存储多个地址的临时存储器部分设置在地址总线侧，并且保存地址以进行每次访问主存储部分不管数据传输，从而流水线地址输入周期。此外，为了主存储器部分的有效操作，使用所保存的地址，地址被重新排列，使得具有相同行地址的地址彼此连续，或者当没有地址与相同的行地址，彼此不同的存储体彼此变得连续，并且此后访问存储器。这减少了预充电次数，缩短了预充电所需的待机时间，并实现了访问，同时减少了浪费时间的使用。

8. 发明授权

US5654913A Apparatus and method for extending data retention time of semiconductor storage circuit 失效
标题翻译：用于延长半导体存储电路的数据保留时间的装置和方法
公开(公告)号：US5654913A
公开(公告)日：1997-08-05
申请号：US597250
申请日：1996-02-06
申请人： Tetsuyuki Fukushima , Hiroyuki Yamauchi , Toru Iwata
发明人： Tetsuyuki Fukushima , Hiroyuki Yamauchi , Toru Iwata
IPC分类号： G11C11/4074 , G11C11/408 , G11C11/24
CPC分类号： G11C11/4074 , G11C11/4085
摘要： In halt period during standby time, a cell plate node potential switching circuit changes the potential of a cell plate node to a low potential that is lower than a high potential adopted in a burst refresh operation. As a result, a potential difference between both ends of a PN junction of a memory cell transistor is decreased, thereby suppressing a leakage current flowing through the PN junction. Simultaneously, a word driver circuit changes the potential of a word line to a negative potential that is lower than a normal potential adopted in the burst refresh operation. As a result, an off state of the memory cell transistor is enhanced owing to decrease of a gate-source voltage thereof, thereby suppressing a leakage current flowing from the bit line to a charge storage node. Accordingly, a leakage current flowing through the PN junction of the memory cell transistor and a leakage current flowing from the bit line through the memory cell transistor to the charge storage node are both suppressed during the standby time. Thus, a refresh interval is elongated so as to decrease power consumption.
摘要翻译：在待机时间期间，电池板节点电位切换电路将电池板节点的电位改变为低于突发刷新操作中采用的高电位的低电位。结果，存储单元晶体管的PN结的两端之间的电位差减小，从而抑制流过PN结的漏电流。同时，字驱动器电路将字线的电位改变为低于突发刷新操作中采用的正常电位的负电位。结果，由于栅极 - 源极电压的降低，存储单元晶体管的截止状态被增强，从而抑制从位线流向电荷存储节点的漏电流。因此，在待机时间期间，都会抑制流过存储单元晶体管的PN结的漏电流和从存储单元晶体管的位线流向电荷存储节点的漏电流。因此，延长刷新间隔以降低功耗。

9. 发明授权

US5652729A Semiconductor integrated circuit apparatus and method of adjusting refresh timer cycle 失效
标题翻译：半导体集成电路设备及其调整刷新定时器周期的方法
公开(公告)号：US5652729A
公开(公告)日：1997-07-29
申请号：US597256
申请日：1996-02-06
申请人： Toru Iwata , Hiroyuki Yamauchi
发明人： Toru Iwata , Hiroyuki Yamauchi
IPC分类号： G11C11/406 , G11C13/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40626 , G11C2211/4068
摘要： A semiconductor Integrated circuit apparatus that has memory cell array, and a refresh timer which outputs a refresh signal for holding data of the memory cell array. The apparatus also has a leak monitoring circuit for detecting a voltage drop associated with a leak current from the memory cell array of a main memory, and a pulse generating circuit for outputting the refresh signal. The leak monitoring circuit is formed by a dummy memory cell array, which is formed by memory cells having the same structure as the memory cells of the main memory, a potential comparator for comparing a potential which is outputted from the dummy memory cell array with a predetermined potential, and leak accelerating means for accelerating the potential decrease speed of the dummy memory cell array.
摘要翻译：具有存储单元阵列的半导体集成电路装置和输出用于保持存储单元阵列的数据的刷新信号的刷新定时器。该装置还具有用于检测与来自主存储器的存储单元阵列的泄漏电流相关联的电压降的泄漏监测电路和用于输出刷新信号的脉冲发生电路。泄漏监视电路由虚拟存储单元阵列形成，该虚拟存储单元阵列由具有与主存储器的存储单元相同结构的存储单元形成，用于将从虚拟存储单元阵列输出的电位与以及用于加速虚拟存储单元阵列的潜在降低速度的泄漏加速装置。

10. 发明申请

US20070041483A1 Clock recovery circuit 审中-公开
标题翻译：时钟恢复电路
公开(公告)号：US20070041483A1
公开(公告)日：2007-02-22
申请号：US11586587
申请日：2006-10-26
申请人： Toru Iwata , Hiroyuki Yamauchi , Takefumi Yoshikawa
发明人： Toru Iwata , Hiroyuki Yamauchi , Takefumi Yoshikawa
IPC分类号： H03D3/24
CPC分类号： H04L25/45 , H03L7/0807 , H03L7/081 , H03L7/087 , H03L7/0891 , H04L7/033
摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.
摘要翻译：驱动器和接收器提供数据信号，其基于具有常规位模式的串行数据，例如时钟，其包括在调整周期期间彼此交替的1和0，并且基于具有任意的串行数据在调整周期后的转移期间的位模式。占空因数控制器调节驱动器或接收器的数据转换特性，使得从接收器提供的数据信号的占空比在调整周期中等于50％，并且具有被调整的数据转换特性。时钟恢复单元恢复与在传送时段中从接收器提供的数据信号同步的时钟，并且基于来自数据信号的经调整的转换特性。

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