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1. 发明授权

US07420833B2 Memory 有权
标题翻译：记忆
公开(公告)号：US07420833B2
公开(公告)日：2008-09-02
申请号：US10936593
申请日：2004-09-09
申请人： Toru Dan , Naofumi Sakai , Shigeharu Matsushita , Yoshiyuki Ishizuka
发明人： Toru Dan , Naofumi Sakai , Shigeharu Matsushita , Yoshiyuki Ishizuka
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to single application of a voltage applied to a nonselected memory cell in the access.
摘要翻译：提供了能够抑制导致非选择存储单元中的数据消失的存储器。该存储器包括存储单元阵列，其包括位线，与位线相交的字线和连接在位线和字线之间的存储单元，用于访问选定的存储单元，从而降低任意存储器中的剩余极化然后在执行写入操作之后立即恢复所有存储器单元以恢复所有存储器单元以进行恢复，以在单次施加施加到访问中的非选择存储单元的电压之后执行剩余极化。

2. 发明申请

US20050068809A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20050068809A1
公开(公告)日：2005-03-31
申请号：US10936593
申请日：2004-09-09
申请人： Toru Dan , Naofumi Sakai , Shigeharu Matsushita , Yoshiyuki Ishizuka
发明人： Toru Dan , Naofumi Sakai , Shigeharu Matsushita , Yoshiyuki Ishizuka
IPC分类号： G11C7/02 , G11C11/22 , G11C16/06 , G11C16/04 , G11C11/34
CPC分类号： G11C11/22
摘要： A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to single application of a voltage applied to a nonselected memory cell in the access.
摘要翻译：提供了能够抑制导致非选择存储单元中的数据消失的存储器。该存储器包括存储单元阵列，其包括位线，与位线相交的字线和连接在位线和字线之间的存储单元，用于访问选定的存储单元，从而降低任意存储器中的剩余极化然后在执行写入操作之后立即恢复所有存储器单元以恢复所有存储器单元以进行恢复，以在单次施加施加到访问中的非选择存储单元的电压之后执行剩余极化。

3. 发明授权

US07652908B2 Ferroelectric memory having a refresh control circuit capable of recovering residual polarization of unselected memory cells 有权
标题翻译：铁电存储器具有能够恢复未选择的存储单元的剩余极化的刷新控制电路
公开(公告)号：US07652908B2
公开(公告)日：2010-01-26
申请号：US11630851
申请日：2005-06-16
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array (1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells (12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell (12). During this access operation, it is performed to apply to the memory cell (12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell (12).
摘要翻译：可以抑制其中未选择的存储单元中的数据丢失的任何“干扰效应”的存储器。该存储器具有存储单元阵列（1），该存储单元阵列（1）包括位线，设置成与位线相交的字线以及各自连接在位线和字线之间的存储单元（12）。在该存储器中，对选择的存储器单元（12）进行包括读取，重写和写入操作中的至少一个的访问操作。在该访问操作期间，执行向存储器单元（12）施加第一电压脉冲，该第一电压脉冲在第一方向上提供电场以反转存储的数据，以及第二电压脉冲，其提供为电场与第一个方向相反的方向，以便不反转存储的数据。此外，对存储单元（12）进行用于恢复残留极化量的恢复操作。

4. 发明授权

US07366004B2 Memory 有权
标题翻译：记忆
公开(公告)号：US07366004B2
公开(公告)日：2008-04-29
申请号：US11328223
申请日：2006-01-10
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.
摘要翻译：提供了能够抑制数据读取中的读取电压的降低而不管制造过程中的分散性的存储器。该存储器包括电荷存储装置，第一场效应晶体管和数据确定装置。存储器将第一场效应晶体管的控制端子和剩余的第一端子之间的电压设置为阈值电压，以使第一场效应晶体管处于ON和OFF之间的边界状态附近的截止状态 - 通过第一场效应晶体管的阈值电压。

5. 发明申请

US20060164877A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20060164877A1
公开(公告)日：2006-07-27
申请号：US11328223
申请日：2006-01-10
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.
摘要翻译：提供了能够抑制数据读取中的读取电压的降低而不管制造过程中的分散性的存储器。该存储器包括电荷存储装置，第一场效应晶体管和数据确定装置。存储器将第一场效应晶体管的控制端子和剩余的第一端子之间的电压设置为阈值电压，以使第一场效应晶体管处于ON和OFF之间的边界状态附近的截止状态 - 通过第一场效应晶体管的阈值电压。

6. 发明申请

US20050057958A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20050057958A1
公开(公告)日：2005-03-17
申请号：US10935554
申请日：2004-09-08
申请人： Hideaki Miyamoto , Yoshiyuki Ishizuka , Naofumi Sakai
发明人： Hideaki Miyamoto , Yoshiyuki Ishizuka , Naofumi Sakai
IPC分类号： G11C16/12 , G11C11/22 , G11C16/24
CPC分类号： G11C11/22
摘要： A memory capable of suppressing disturbance is provided. This memory activates each of a selected word line and a bit line corresponding to unrewritten storage means while keeping potential difference therebetween at a level not more than a prescribed value and differentiates the length of a period for applying a voltage for rewriting to each of the selected word line and a bit line corresponding to rewritten storage means from the length of a transition period of the potential of at least either the word line or the bit line corresponding to the unrewritten storage means when performing a rewrite operation on partial selected storage means or performing no rewrite operation on all selected storage means.
摘要翻译：提供了能够抑制干扰的存储器。该存储器激活对应于未启动存储装置的所选字线和位线中的每一个，同时保持它们之间的电位差不超过规定值，并且将用于重写的电压的周期长度区分为所选择的每一个字线和对应于重写存储装置的位线，当对部分选择的存储装置执行重写操作时，从对应于未刷新存储装置的字线或位线中的至少一个的电位的转变周期的长度的长度，对所有选定的存储装置不进行重写操作。

7. 发明申请

US20070237016A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20070237016A1
公开(公告)日：2007-10-11
申请号：US11630851
申请日：2005-06-16
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C7/00
CPC分类号： G11C11/22
摘要： A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array(1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells(12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell(12). During this access operation, it is performed to apply to the memory cell(12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell(12).
摘要翻译：可以抑制其中未选择的存储单元中的数据丢失的任何“干扰效应”的存储器。该存储器具有存储单元阵列（1），该存储单元阵列（1）包括位线，设置成与位线相交的字线以及每个连接在位线和字线之间的存储单元（12）。在该存储器中，对选择的存储器单元（12）进行包括读取，重写和写入操作中的至少一个的访问操作。在该访问操作期间，执行向存储器单元（12）施加第一电压脉冲，该第一电压脉冲在第一方向上提供电场以反转存储的数据，以及第二电压脉冲，其提供为电场与第一个方向相反的方向，以便不反转存储的数据。此外，对存储单元（12）进行用于恢复残留极化量的恢复操作。

8. 发明申请

US20050052914A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20050052914A1
公开(公告)日：2005-03-10
申请号：US10932081
申请日：2004-09-02
申请人： Hideaki Miyamoto , Naofumi Sakai , Yoshiyuki Ishizuka
发明人： Hideaki Miyamoto , Naofumi Sakai , Yoshiyuki Ishizuka
IPC分类号： H01L27/10 , G11C5/02 , G11C11/00 , G11C11/22 , H01L21/8246 , H01L27/105
CPC分类号： G11C5/025 , G11C11/22
摘要： A semiconductor memory device allowing miniaturization is provided. This semiconductor memory device comprises a word line and a bit line arranged to intersect with each other, a memory cell array region including a plurality of memory cells connected to the word line and the bit line and a transfer gate transistor arranged under the memory cell array region.
摘要翻译：提供允许小型化的半导体存储器件。这种半导体存储器件包括一个字线和位线相互交叉排列，一个存储单元阵列区域包括连接到该字线和该位线的多个存储单元，以及一个布置在该存储单元阵列下面的一个传输门晶体管地区。

9. 发明授权

US07110279B2 Memory 有权
标题翻译：记忆
公开(公告)号：US07110279B2
公开(公告)日：2006-09-19
申请号：US10935554
申请日：2004-09-08
申请人： Hideaki Miyamoto , Yoshiyuki Ishizuka , Naofumi Sakai
发明人： Hideaki Miyamoto , Yoshiyuki Ishizuka , Naofumi Sakai
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C11/22
摘要： A memory capable of suppressing disturbance is provided. This memory activates each of a selected word line and a bit line corresponding to unrewritten storage means while keeping potential difference therebetween at a level not more than a prescribed value and differentiates the length of a period for applying a voltage for rewriting to each of the selected word line and a bit line corresponding to rewritten storage means from the length of a transition period of the potential of at least either the word line or the bit line corresponding to the unrewritten storage means when performing a rewrite operation on partial selected storage means or performing no rewrite operation on all selected storage means.
摘要翻译：提供了能够抑制干扰的存储器。该存储器激活对应于未启动存储装置的选定字线和位线中的每一个，同时保持它们之间的电位差不超过规定值，并且将用于重写的电压的周期长度区分为所选择的每一个字线和对应于重写存储装置的位线，当对部分选择的存储装置执行重写操作时，从对应于未刷新存储装置的字线或位线中的至少一个的电位的转变周期的长度的长度，对所有选定的存储装置不进行重写操作。

10. 发明申请

US20050152193A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20050152193A1
公开(公告)日：2005-07-14
申请号：US11024688
申请日：2004-12-30
申请人： Naofumi Sakai
发明人： Naofumi Sakai
IPC分类号： G11C11/22 , G11C11/409 , H01L27/105
CPC分类号： G11C11/22
摘要： A memory capable of suppressing disturbance causing disappearance of data from a nonselected memory cell is provided. This memory applies a second voltage of polarity reverse to that of a first voltage applied to a nonselected memory cell in a read operation to at least the nonselected memory cell in addition to the read operation collectively performed on all memory cells connected to a selected word line.
摘要翻译：提供一种能够抑制导致来自非选择存储单元的数据消失的干扰的存储器。除了对连接到所选择的字线的所有存储器单元上共同执行的读取操作之外，该存储器将至少非选择存储器单元的读取操作中施加到非选择存储单元的第一电压的极性的第二电压与第一电压相反。

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