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1. 发明授权

US5963736A Software reconfigurable target I/O in a circuit emulation system 失效
标题翻译：电路仿真系统中的软件可重构目标I / O
公开(公告)号：US5963736A
公开(公告)日：1999-10-05
申请号：US805852
申请日：1997-03-03
申请人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Curt Blanding
发明人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Curt Blanding
IPC分类号： G06F11/22 , G06F11/26 , G06F17/50 , G06F9/455
CPC分类号： G06F17/5027 , G06F11/261
摘要： A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator is connected to a target system via a Pod System Interface (PSI), a specially designed cable, and a Pod User Interface (PUI). For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator. The cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator. For data traveling from the target system to the emulator, each PUI receives up to 128 bits of data from the target system. Each PUI sends four groups of 32 bits in accordance with a fast clock signal. Each PSI receives the groups of 32 bits and holds them in an internal register, sending the received bits to the emulator under control of the emulator.
摘要翻译：时间分片的基于硬件的仿真器，其包括以下中的至少一个：可编程I / O分配; 可编程电平的直流电压; 以引脚为基础在仿真器中编程上拉或下拉电阻; 可编程强制和/或禁用每个引脚上仿真器的值输出; 可编程时钟; 和可编程采样模式。仿真器通过Pod系统接口（PSI），专门设计的电缆和Pod用户界面（PUI）连接到目标系统。对于从仿真器传输到目标系统的数据，每个PSI从仿真器接收高达128位的数据。然而，电缆只有32位宽。因此，仿真器将通过电缆发送的数据进行多路复用，根据快速时钟信号向PC发送8位交错的32位组。每个PUI从PSI接收32位的组，并根据来自仿真器的控制信号将它们发送到目标系统。对于从目标系统传输到仿真器的数据，每个PUI从目标系统接收高达128位的数据。每个PUI根据快速时钟信号发送四组32位。每个PSI接收32位组并将它们保存在一个内部寄存器中，在仿真器的控制下将接收到的位发送到仿真器。

2. 发明申请

US20070069148A1 Beam blanker driver system and method 失效
标题翻译：光束遮挡器驱动系统及方法
公开(公告)号：US20070069148A1
公开(公告)日：2007-03-29
申请号：US11236885
申请日：2005-09-28
申请人： Curt Blanding , Scott Stovall
发明人： Curt Blanding , Scott Stovall
IPC分类号： H01J37/147
CPC分类号： H01J37/24 , H01J37/045 , H01J2237/3175
摘要： A particle beam lithography system and method of blanking a beam such as a particle or other beam. The system may include a frequency divider adapted to convert a master clock signal at a first frequency into an integral number N of waveforms at a second frequency, a reference device adapted to provide a fixed threshold reference signal, a sequencer adapted to provide N sets of data, a blanking circuit for each of the waveforms for creating a blanking signal for each of the waveforms, and a logic circuit for combining each of the blanking signals from each of the blanking circuits. The blanking circuit may include a digital to analog converter adapted to receive one of the N sets of data from the sequencer and to generate a variable threshold reference signal and a window comparator adapted to receive one of the waveforms, the fixed threshold reference signal, and the variable threshold reference signal and to generate a blanking signal.
摘要翻译：一种粒子束光刻系统和消除诸如粒子或其他光束的光束的方法。该系统可以包括适于将第一频率的主时钟信号转换为第二频率的整数N个波形的分频器，适于提供固定阈值参考信号的参考装置，适于提供N组数据，用于为每个波形创建消隐信号的每个波形的消隐电路，以及用于组合来自每个消隐电路的每个消隐信号的逻辑电路。消隐电路可以包括数模转换器，其适于从定序器接收N组数据中的一个并产生可变阈值参考信号，并且窗口比较器适于接收波形之一，固定阈值参考信号和可变阈值参考信号并产生消隐信号。

3. 发明授权

US07265361B2 Beam blanker driver system and method 失效
公开(公告)号：US07265361B2
公开(公告)日：2007-09-04
申请号：US11236885
申请日：2005-09-28
申请人： Curt Blanding , Scott C. Stovall
发明人： Curt Blanding , Scott C. Stovall
IPC分类号： H01J37/47 , B01D15/08
CPC分类号： H01J37/24 , H01J37/045 , H01J2237/3175
摘要： A particle beam lithography system and method of blanking a beam such as a particle or other beam. The system may include a frequency divider adapted to convert a master clock signal at a first frequency into an integral number N of waveforms at a second frequency, a reference device adapted to provide a fixed threshold reference signal, a sequencer adapted to provide N sets of data, a blanking circuit for each of the waveforms for creating a blanking signal for each of the waveforms, and a logic circuit for combining each of the blanking signals from each of the blanking circuits. The blanking circuit may include a digital to analog converter adapted to receive one of the N sets of data from the sequencer and to generate a variable threshold reference signal and a window comparator adapted to receive one of the waveforms, the fixed threshold reference signal, and the variable threshold reference signal and to generate a blanking signal.

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