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1. 发明申请

US20100249771A1 SYSTEM AND METHOD FOR INTERACTIVELY PLANNING AND CONTROLLING A TREATMENT OF A PATIENT WITH A MEDICAL TREATMENT DEVICE 审中-公开
标题翻译：用于交互式计划和控制用医疗治疗装置治疗患者的系统和方法
公开(公告)号：US20100249771A1
公开(公告)日：2010-09-30
申请号：US12751854
申请日：2010-03-31
申请人： Robert M. Pearson , James G. Lovewell , David Warden , David Lee Morrison , Tony R. Sarno , Hy Truong Lai , William C. Hamilton, JR. , Rafael Vidal Davalos , Robert E. Neal, II
发明人： Robert M. Pearson , James G. Lovewell , David Warden , David Lee Morrison , Tony R. Sarno , Hy Truong Lai , William C. Hamilton, JR. , Rafael Vidal Davalos , Robert E. Neal, II
IPC分类号： A61B18/12
CPC分类号： A61B18/1206 , A61B18/148 , A61B34/10 , A61B34/20 , A61B2018/00613 , A61B2018/00684 , A61B2018/00702 , A61B2018/00839 , A61B2034/104 , A61B2034/2063
摘要： A system and method for interactively planning and controlling a treatment of a patient for a medical treatment device are provided. The system includes a memory; a processor coupled to the memory; and a treatment control module stored in the memory and executable by the processor. The treatment control module graphically displays in real time a continuously changing treatment region defined by the electrodes as a user moves at least one of the electrodes. This allows the user to more effectively plan and treat a target region.
摘要翻译：提供了用于交互地规划和控制用于医疗处理装置的患者的治疗的系统和方法。该系统包括一个内存; 耦合到存储器的处理器; 以及存储在存储器中并由处理器执行的处理控制模块。当用户移动至少一个电极时，治疗控制模块实时图形地显示由电极限定的连续变化的治疗区域。这允许用户更有效地规划和处理目标区域。

2. 发明申请

US20100250209A1 SYSTEM AND METHOD FOR ESTIMATING A TREATMENT REGION FOR A MEDICAL TREATMENT DEVICE 审中-公开
标题翻译：用于估计医疗处理设备的治疗区域的系统和方法
公开(公告)号：US20100250209A1
公开(公告)日：2010-09-30
申请号：US12751826
申请日：2010-03-31
申请人： Robert M. Pearson , James G. Lovewell , David Warden , David Lee Morrison , Tony R. Sarno , Hy Truong Lai , William C. Hamilton, JR. , Rafael Vidal Davalos , Robert E. Neal, II
发明人： Robert M. Pearson , James G. Lovewell , David Warden , David Lee Morrison , Tony R. Sarno , Hy Truong Lai , William C. Hamilton, JR. , Rafael Vidal Davalos , Robert E. Neal, II
IPC分类号： G06F17/10 , A61B18/12
CPC分类号： A61B18/1206 , A61B18/148 , A61B34/10 , A61B34/20 , A61B2018/00613 , A61B2018/00684 , A61B2018/00702 , A61B2018/00839 , A61B2034/104 , A61B2034/2063
摘要： A medical system and method for estimating a treatment region for a medical treatment device is provided. The system includes a memory; a processor coupled to the memory; and a treatment control module stored in the memory and executable by the processor. The treatment control module generates an estimated treatment region which is an estimate of a treatment region which would have been derived as a result of a numerical model analysis such as a finite element analysis. Advantageously, the estimated treatment region is generated using a fraction of the time it takes to generate the region using the numerical model analysis.
摘要翻译：提供了一种用于估计医疗处理装置的治疗区域的医疗系统和方法。该系统包括一个内存; 耦合到存储器的处理器; 以及存储在存储器中并由处理器执行的处理控制模块。处理控制模块生成作为由诸如有限元分析之类的数值模型分析的结果而导出的处理区域的估计的估计处理区域。有利地，使用数值模型分析使用生成区域所花费的时间的一小部分来生成估计的处理区域。

3. 发明授权

US5819065A System and method for emulating memory 失效
标题翻译：用于模拟内存的系统和方法
公开(公告)号：US5819065A
公开(公告)日：1998-10-06
申请号：US597197
申请日：1996-02-06
申请人： John E. Chilton , Tony R. Sarno , Ingo Schaefer
发明人： John E. Chilton , Tony R. Sarno , Ingo Schaefer
IPC分类号： G06F11/22 , G06F11/26 , G06F17/50 , G06F9/455
CPC分类号： G06F11/261 , G06F17/5027
摘要： A system and method for emulating memory designs is described. The system includes a time sliced logic emulator. The time sliced logic emulator emulates the functions performed in one cycle of a target design by emulating portions of the functions in a set of time slices. That is, a set of time slices represents a single clock cycle in the target design. The system emulates many different types of memory designs included in the target design. The system includes an emulation memory. The memory designs are mapped to the emulation memory via a programmable address generation block. For a given time slice, the programmable address generation block generates an address that maps all or part of a memory design address to an emulation memory address. The programmable address generation block allows multiple memory designs to be mapped to a single emulation memory and allows a single memory design to be mapped to multiple emulation memories. Thus, over multiple time slices, the system can emulate many different types of memories.
摘要翻译：描述了用于模拟存储器设计的系统和方法。该系统包括时间分片逻辑仿真器。时间分片逻辑仿真器通过模拟一组时间片中的部分功能来模拟在目标设计的一个周期中执行的功能。也就是说，一组时间片表示目标设计中的单个时钟周期。该系统模拟目标设计中包含的许多不同类型的存储器设计。该系统包括一个仿真存储器。存储器设计通过可编程地址生成块映射到仿真存储器。对于给定的时间片，可编程地址生成块产生将存储器设计地址的全部或部分映射到仿真存储器地址的地址。可编程地址生成块允许将多个存储器设计映射到单个仿真存储器，并允许将单个存储器设计映射到多个仿真存储器。因此，在多个时间片上，系统可以模拟许多不同类型的存储器。

4. 发明授权

US5963736A Software reconfigurable target I/O in a circuit emulation system 失效
标题翻译：电路仿真系统中的软件可重构目标I / O
公开(公告)号：US5963736A
公开(公告)日：1999-10-05
申请号：US805852
申请日：1997-03-03
申请人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Curt Blanding
发明人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Curt Blanding
IPC分类号： G06F11/22 , G06F11/26 , G06F17/50 , G06F9/455
CPC分类号： G06F17/5027 , G06F11/261
摘要： A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator is connected to a target system via a Pod System Interface (PSI), a specially designed cable, and a Pod User Interface (PUI). For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator. The cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator. For data traveling from the target system to the emulator, each PUI receives up to 128 bits of data from the target system. Each PUI sends four groups of 32 bits in accordance with a fast clock signal. Each PSI receives the groups of 32 bits and holds them in an internal register, sending the received bits to the emulator under control of the emulator.
摘要翻译：时间分片的基于硬件的仿真器，其包括以下中的至少一个：可编程I / O分配; 可编程电平的直流电压; 以引脚为基础在仿真器中编程上拉或下拉电阻; 可编程强制和/或禁用每个引脚上仿真器的值输出; 可编程时钟; 和可编程采样模式。仿真器通过Pod系统接口（PSI），专门设计的电缆和Pod用户界面（PUI）连接到目标系统。对于从仿真器传输到目标系统的数据，每个PSI从仿真器接收高达128位的数据。然而，电缆只有32位宽。因此，仿真器将通过电缆发送的数据进行多路复用，根据快速时钟信号向PC发送8位交错的32位组。每个PUI从PSI接收32位的组，并根据来自仿真器的控制信号将它们发送到目标系统。对于从目标系统传输到仿真器的数据，每个PUI从目标系统接收高达128位的数据。每个PUI根据快速时钟信号发送四组32位。每个PSI接收32位组并将它们保存在一个内部寄存器中，在仿真器的控制下将接收到的位发送到仿真器。

5. 发明授权

US6141636A Logic analysis subsystem in a time-sliced emulator 失效
标题翻译：时分片仿真器中的逻辑分析子系统
公开(公告)号：US6141636A
公开(公告)日：2000-10-31
申请号：US831501
申请日：1997-03-31
申请人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Bernard Y. Chan , Michael C. Tsou
发明人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Bernard Y. Chan , Michael C. Tsou
IPC分类号： G06F17/50 , G06F11/25 , G06F11/26 , G06F11/34 , G06F9/455
CPC分类号： G06F11/261 , G06F11/25 , G06F11/3466
摘要： A logic analysis subsystem in a time-sliced emulator. The logic analysis subsystem "reconstructs" signals that were previously reduced by the compiler and allows the user to set breakpoints and triggers using these and other signals of the emulated circuit. The present invention includes a "logic analysis subsystem compiler" and "logic analysis subsystem hardware." The logic analysis subsystem compiler is either a subpart of the regular emulator compiler or is a standalone compiler. It compiles the design to be emulated and generates control instructions for the logic analysis subsystem hardware. The logic analysis subsystem hardware is incorporated into the time-sliced emulator to receive signals generated by the emulator during emulation. When the logic analysis subsystem operates, the control instructions cause the logic analysis subsystem to reconstruct previously reduced signals received from the emulator. These signals (along with the signals received from the emulator) may be used by the user to set breakpoints and triggers in the logic analysis subsystem.
摘要翻译：时间分片仿真器中的逻辑分析子系统。逻辑分析子系统“重建”先前由编译器减少的信号，并允许用户使用仿真电路的这些和其他信号来设置断点和触发。本发明包括“逻辑分析子系统编译器”和“逻辑分析子系统硬件”。逻辑分析子系统编译器是常规仿真器编译器的子部分，也可以是独立编译器。它编译要仿真的设计，并为逻辑分析子系统硬件生成控制指令。逻辑分析子系统硬件被并入到时间分割的仿真器中，以在仿真期间接收由仿真器产生的信号。当逻辑分析子系统运行时，控制指令使逻辑分析子系统重建从仿真器接收的先前减小的信号。这些信号（以及从仿真器接收到的信号）可以由用户用于在逻辑分析子系统中设置断点和触发器。

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