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1. 发明授权

US6100191A Method for forming self-aligned silicide layers on sub-quarter micron VLSI circuits 失效
标题翻译：在二分之一微米VLSI电路上形成自对准硅化物层的方法
公开(公告)号：US6100191A
公开(公告)日：2000-08-08
申请号：US59687
申请日：1998-04-14
申请人： Tony Lin , Water Lur , Jiun-Yuan Wu , Hsiao-Lin Lu
发明人： Tony Lin , Water Lur , Jiun-Yuan Wu , Hsiao-Lin Lu
IPC分类号： H01L21/285 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/2855
摘要： The present invention discloses a method to manufacture a self-aligned silicide layer on a substrate. A metal oxide semiconductor (MOS) device and a shallow trench are fabricated in the substrate. The device has a gate structure, spacers of the gate structured and doping regions. The shallow trench is refilled with silicon oxide material for isolation. A silicon layer is nonconformally deposited on the top surface of the gate structure, the spacers and the doping regions by using a physical vapor deposition (PVD) process, such as ion metal plasma (IMP) process. The IMP process, like a sputtering process, is to ionize a silicon material or a refractory-metal material to silicon ions or metal ions and the ions are biased to anisotropically deposit on the top surface of the substrate. A refractory metal layer is defined on the top surface of the silicon layer by the IMP technology. A two-step thermal annealing process, such as rapid thermal annealing (RTA) process is performed to convert the silicon layer and the refractory metal layer into a silicide layer. Since the silicon layer serves as a silicon source for the salicide process, the silicide layer can form on the spacers and the silicon oxide material of the trench.
摘要翻译：本发明公开了一种在衬底上制造自对准硅化物层的方法。在衬底中制造金属氧化物半导体（MOS）器件和浅沟槽。器件具有栅极结构，栅极结构和掺杂区域的间隔物。浅沟槽用氧化硅材料再填充以进行隔离。通过使用诸如离子金属等离子体（IMP）工艺的物理气相沉积（PVD）工艺，硅层不均匀地沉积在栅极结构，间隔物和掺杂区域的顶表面上。 IMP工艺，如溅射工艺，是将硅材料或难熔金属材料离子化成硅离子或金属离子，并将离子偏置成各向异性沉积在衬底的顶表面上。难熔金属层通过IMP技术限定在硅层的顶表面上。进行两步热退火处理，例如快速热退火（RTA）工艺，以将硅层和难熔金属层转化为硅化物层。由于硅层用作自对准硅化物工艺的硅源，硅化物层可以形成在间隔物和沟槽的氧化硅材料上。

2. 发明授权

US5739046A Method of making a reliable barrier layer 失效
标题翻译：制作可靠屏障层的方法
公开(公告)号：US5739046A
公开(公告)日：1998-04-14
申请号：US657058
申请日：1996-05-28
申请人： Water Lur , Shih-Chanh Chang , Jiun Yuan Wu , Der Yuan Wu
发明人： Water Lur , Shih-Chanh Chang , Jiun Yuan Wu , Der Yuan Wu
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76864 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76856
摘要： A new method of forming a metal diffusion barrier layer is described. Semiconductor device structures are formed in and on a semiconductor substrate. At least one dielectric layer covers the semiconductor structures and at least one contact hole has been opened through the dielectric layer(s) to the semiconductor substrate. A metal diffusion barrier layer is now formed using the following steps: In the first step, a thin layer of titanium is deposited conformally over the surface of the dielectric layer(s) and within the contact opening(s) and annealed in a nitrogen atmosphere at a temperature of between about 580.degree. to 630.degree. C. for between about 20 to 120 seconds. The second step is to form stable and adhesive titanium compounds on the pre-metal dielectric layer as well as to form a low resistance silicide on the contact silicon by annealing at between about 800.degree. to 900.degree. C. for between about 5 to 60 seconds. The final step is to release the system stress by tempering the layer at a temperature of between about 600.degree. to 750.degree. C. This completes the barrier layer which has good adhesion to the dielectric layer(s) and, therefore, promotes improved pad bonding yield.
摘要翻译：描述形成金属扩散阻挡层的新方法。在半导体衬底中形成半导体器件结构。至少一个电介质层覆盖半导体结构，并且至少一个接触孔已经通过介电层被打开到半导体衬底。现在通过以下步骤形成金属扩散阻挡层：在第一步骤中，将薄的钛层保形地沉积在电介质层的表面和接触开口内，并在氮气气氛中退火在约580℃至630℃之间的温度下进行约20至120秒。第二步是在金属前介电层上形成稳定且粘合的钛化合物，并在接触硅上形成低电阻硅化物，在约800-900℃之间退火约5至60秒。最后一步是通过在约600至750℃的温度下回火层来释放系统应力。这完成了与电介质层具有良好粘附性的阻挡层，因此促进改进的焊盘接合产量。

3. 发明授权

US5828134A Metallization to improve electromigration resistance 失效
标题翻译：金属化以提高电迁移率
公开(公告)号：US5828134A
公开(公告)日：1998-10-27
申请号：US746436
申请日：1996-11-08
申请人： Water Lur , Jiun Yuan Wu
发明人： Water Lur , Jiun Yuan Wu
IPC分类号： H01L21/768 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/48 , H01L23/52
CPC分类号： H01L23/485 , H01L21/76804 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S148/161 , Y10S438/927 , Y10S438/978
摘要： A new method of metallization using a new design of metal contact shape, contact/via profile, and metal lines having considerably reduced current density and improved electromigration of metal lines is achieved. Metal contacts are formed in a rectangular shape instead of a square shape with the wider side perpendicular to the current direction. Contact openings are made having concavo-concave profiles which can provide a wider conducting cross-sectional area than can conventional openings with a vertical profile near the contact bottom. Gaps are formed within wide and high current metal lines so that current density can be effectively lowered by utilizing the whole metal line uniformly.
摘要翻译：实现了使用金属接触形状，接触/通孔轮廓和金属线的新设计的金属化的新方法，其具有显着降低的电流密度和改善金属线的电迁移。金属触点形成为矩形形状而不是具有与电流方向垂直的较宽侧的正方形形状。接触开口被制成具有凹形轮廓，其可以提供比具有接触底部附近的垂直轮廓的常规开口更宽的导电横截面面积。在宽且高电流的金属线中形成间隙，通过均匀地利用整个金属线，可以有效地降低电流密度。

4. 发明授权

US6069061A Method for forming polysilicon gate 有权
标题翻译：多晶硅栅极形成方法
公开(公告)号：US6069061A
公开(公告)日：2000-05-30
申请号：US245648
申请日：1999-02-08
申请人： Tony Lin , Water Lur
发明人： Tony Lin , Water Lur
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49
CPC分类号： H01L29/4933 , H01L21/28052 , H01L29/6659
摘要： A method is provided for forming a polysilicon gate. A stacked gate with a first polysilicon layer/an oxide layer/a second polysilicon layer multiple structure is formed. The invention provides another method for forming a polysilicon gate, in which a first polysilicon layer is formed and waits for a period of time. Then, a second polysilicon layer is formed on the first polysilicon layer. A grain boundary is formed between the first polysilicon layer and the second polysilicon layer. The invention provides still another method for forming a polysilicon gate, in which a polysilicon layer is formed at the temperature of about 600-700.degree. C. and the pressure of about 1-5 torr to form a small-grained polysilicon layer. The three methods for forming a polysilicon gate can prevent the heavy ions from passing through the polysilicon gate and the gate oxide layer into the substrate while performing a pre-amorphization implant process. The absence of these heavy ions in the substrate avoids the subthreshold kink side-effect.
摘要翻译：提供了形成多晶硅栅极的方法。形成具有第一多晶硅层/氧化物层/第二多晶硅层多重结构的堆叠栅极。本发明提供了形成多晶硅栅极的另一种方法，其中形成第一多晶硅层并等待一段时间。然后，在第一多晶硅层上形成第二多晶硅层。在第一多晶硅层和第二多晶硅层之间形成晶界。本发明提供另一种形成多晶硅栅极的方法，其中在约600-700℃的温度和约1-5托的压力下形成多晶硅层以形成小粒度多晶硅层。用于形成多晶硅栅极的三种方法可以防止重离子在进行预非晶化注入工艺时通过多晶硅栅极和栅极氧化物层进入衬底。衬底中没有这些重离子避免了亚阈值扭结副作用。

5. 发明授权

US5874353A Method of forming a self-aligned silicide device 失效
标题翻译：形成自对准硅化物器件的方法
公开(公告)号：US5874353A
公开(公告)日：1999-02-23
申请号：US927321
申请日：1997-09-11
申请人： Tony Lin , Water Lur , Shih-Wei Sun
发明人： Tony Lin , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28061 , H01L29/4925 , H01L29/4941
摘要： A method of forming self-aligned silicide devices which includes providing a silicon substrate having shallow trench isolation regions for defining a device area formed therein; then, forming sequentially a gate oxide layer, a polysilicon layer, a first titanium nitride layer, a titanium silicide layer, a second titanium nitride layer and a silicon nitride layer over the substrate. After a gate electrode is etched out from the above layers, a titanium layer is deposited over the device, and then a self-aligned titanium silicide layer is formed using a heating process. The use of a titanium silicide layer having protective top and bottom titanium nitride layers, compared with a single tungsten silicide layer in a conventional method, provides for a self-aligned silicide device having a rather low gate resistance; being free from narrow width effect of a titanium self-aligned silicide layer; is applicable to self-aligned contact window processes, and avoids the cross-diffusion of doped ions in the polysilicon layer of a dual gate electrode having a tungsten polycide layer.
摘要翻译：一种形成自对准硅化物器件的方法，其包括提供具有浅沟槽隔离区域的硅衬底，用于限定其中形成的器件区域; 然后在衬底上依次形成栅氧化层，多晶硅层，第一氮化钛层，硅化钛层，第二氮化钛层和氮化硅层。在从上述层蚀刻出栅电极之后，在器件上沉积钛层，然后使用加热工艺形成自对准硅化钛层。与常规方法中的单个硅化钨层相比，使用具有保护性顶部和底部氮化钛层的硅化钛层提供具有相当低的栅极电阻的自对准硅化物器件; 没有钛自对准硅化物层的窄宽度效应; 适用于自对准接触窗工艺，并避免掺杂离子在具有钨多硅化物层的双栅电极的多晶硅层中的交叉扩散。

6. 发明授权

US6025241A Method of fabricating semiconductor devices with self-aligned silicide 失效
标题翻译：制造具有自对准硅化物的半导体器件的方法
公开(公告)号：US6025241A
公开(公告)日：2000-02-15
申请号：US73576
申请日：1998-05-06
申请人： Tony Lin , Water Lur
发明人： Tony Lin , Water Lur
IPC分类号： H01L21/3115 , H01L21/336 , H01L21/28
CPC分类号： H01L29/66507 , H01L29/6659 , H01L21/31155 , Y10S148/147
摘要： A method for fabricating a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor, with self-aligned silicide is provided. This method can prevent junction leakage between the silicide and the substrate so as to allow the resultant semiconductor device to have reliable performance. The method includes the steps of preparing a semiconductor substrate; forming at least one transistor element over the substrate, the transistor element including a pair of source/drain regions, a gate, a dielectric layer over the gate, and a spacer on the sidewall of the gate; and performing an ion-bombardment process so as to transport one part of the dielectric layer that is adjacent to the top of the spacer to beside the bottom of the spacer. Through this method, the resultant semiconductor device is reliable in operation since the drawback of the occurrence of leakage current or short-circuit that could be otherwise resulted between the self-aligned silicide and the substrate owing to the short-channel effect can be eliminated. Moreover, the resultant semiconductor device has increased anti-static capability that can protect the semiconductor device against electro-static damage.
摘要翻译：提供了一种用于制造具有自对准硅化物的半导体器件（例如MOS（金属氧化物半导体）晶体管）的方法。该方法可以防止硅化物与衬底之间的结漏电，从而使所得的半导体器件具有可靠的性能。该方法包括制备半导体衬底的步骤; 在所述衬底上形成至少一个晶体管元件，所述晶体管元件包括一对源极/漏极区域，栅极，所述栅极上的电介质层以及所述栅极侧壁上的间隔物; 并且进行离子轰击处理，以将邻近间隔物顶部的电介质层的一部分输送到间隔物的底部旁边。通过该方法，由于短沟道效应，可以消除由于短路导致的自对准硅化物和衬底之间的漏电流或短路的缺点，所以得到的半导体器件工作可靠。此外，所得到的半导体器件具有增强的抗静电能力，可以保护半导体器件免受静电损坏。

7. 发明授权

US6015741A Method for forming self-aligned contact window 失效
标题翻译：用于形成自对准接触窗的方法
公开(公告)号：US6015741A
公开(公告)日：2000-01-18
申请号：US59428
申请日：1998-04-13
申请人： Tony Lin , Water Lur , Shih-Wei Sun
发明人： Tony Lin , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/336 , H01L21/60 , H01L21/44
CPC分类号： H01L21/76897 , H01L29/665
摘要： A method for forming a self-aligned contact window such that the method is compatible with the process of forming a self-aligned titanium silicide layer on the same device, and hence capable of miniaturizing device dimensions. Furthermore, this invention utilizes the thicker etching stop layer thickness above the gate region than above the source/drain region to protect the titanium silicide layer in the gate region against electrical contact with the self-aligned contact.
摘要翻译：一种用于形成自对准接触窗的方法，使得该方法与在同一器件上形成自对准钛硅化物层的工艺兼容，因此能够使器件尺寸小型化。此外，本发明利用栅极区域之上的栅极区域之上的厚度超过源极/漏极区域的厚度，以保护栅极区域中的硅化钛层免受与自对准接触件的电接触。

8. 发明授权

US6001738A Method of forming salicide 失效
标题翻译：形成自杀剂的方法
公开(公告)号：US6001738A
公开(公告)日：1999-12-14
申请号：US62115
申请日：1998-04-17
申请人： Tony Lin , Water Lur , Shih-Wei Sun
发明人： Tony Lin , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/336 , H01L21/283
CPC分类号： H01L29/6659 , H01L29/665
摘要： A method of forming salicide, of which the characteristics is the formation of a silicon nitride layer before the source/drain being implanted with dopant. The silicon nitride layer avoid the oxygen within the oxide layer to implant into the source/drain. Thus, a better salicide is obtained. In addition, the formation of the parasitic spacers made of silicon nitride at the side wall bottom of the gate spacer increases the distance between the salicide and the junction. Consequently, the leakage current is prevented. While the silicon nitride layer is removed, the polysilicon of gate and the silicon of the source/drain are amorphized. This is advantageous to the formation of salicide without the step of ion implantation.
摘要翻译：一种形成硅化物的方法，其特征是在掺杂有掺杂剂的源极/漏极之前形成氮化硅层。氮化硅层避免氧化物层内的氧气注入到源极/漏极中。因此，获得更好的自杀剂。此外，在栅极间隔物的侧壁底部由氮化硅制成的寄生间隔物的形成增加了自对准硅化物与接合部之间的距离。因此，防止漏电流。当去除氮化硅层时，栅极和源极/漏极的硅的多晶硅是非晶化的。这对于没有离子注入步骤的硅化物的形成是有利的。

9. 发明授权

US5981383A Method of fabricating a salicide layer of a device electrode 失效
标题翻译：制造器件电极的自对准硅化物层的方法
公开(公告)号：US5981383A
公开(公告)日：1999-11-09
申请号：US814376
申请日：1997-03-11
申请人： Water Lur , Tony Lin
发明人： Water Lur , Tony Lin
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/336 , H01L29/423 , H01L21/70
CPC分类号： H01L29/6659 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L21/3205 , H01L21/32053 , H01L29/665 , H01L29/42376
摘要： Salicide (self-aligned silicide) structures are formed using a process that does not form oxide spacer structures alongside polysilicon gate electrodes and wiring lines. A shaped polysilicon electrode is formed having protrusions extending beyond the sidewalls of the electrode. LDD source/drain regions are formed by ion implantation using only the polysilicon gate electrode as a mask, thereby forming LDD source drain/regions without using spacer oxide regions. Physical vapor deposition is used to deposit a metal layer having discontinuities at or adjacent the protrusions. A first rapid thermal anneal is performed to cause the metal to form a metal silicide over the polysilicon electrode. Unreacted metal is etched and then a second rapid thermal anneal is performed to convert the metal silicide to its lowest resistivity phase. Gate electrodes and wiring lines having this structure generally are formed having lower stress in the silicide layers, producing salicide structures having lower resistance than gate electrodes and wiring lines formed using conventional salicide techniques.
摘要翻译：使用不与多晶硅栅电极和布线一起形成氧化物间隔结构的工艺来形成硅化物（自对准硅化物）结构。形成具有延伸超过电极侧壁的突起的成形多晶硅电极。通过仅使用多晶硅栅极作为掩模的离子注入形成LDD源极/漏极区域，从而在不使用间隔氧化物区域的情况下形成LDD源极漏极/区域。物理气相沉积用于沉积在突起处或邻近突起处具有不连续性的金属层。进行第一快速热退火以使金属在多晶硅电极上形成金属硅化物。蚀刻未反应的金属，然后进行第二次快速热退火，以将金属硅化物转化为最低电阻率相。具有这种结构的栅极电极和布线通常形成为在硅化物层中具有较低的应力，产生具有比栅电极低的电阻和使用常规自对准硅化物技术形成的布线的硅化物结构。

10. 发明授权

US5913124A Method of making a self-aligned silicide 失效
标题翻译：制造自对准硅化物的方法
公开(公告)号：US5913124A
公开(公告)日：1999-06-15
申请号：US883332
申请日：1997-06-26
申请人： Tony Lin , Water Lur
发明人： Tony Lin , Water Lur
IPC分类号： H01L21/28 , H01L21/265 , H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/823418 , H01L21/823443 , H01L29/665 , H01L21/26586
摘要： A method of making a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region. The method includes performing an ion implantation operation at a large tilt angle, which increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The isolating regions are overetched, which exposes the surface of the source/drain regions. The metal silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window, resulting in a lowering of both contact resistance and sheet resistance there.
摘要翻译：一种制造自对准硅化物的方法，该硅化物在与隔离区相邻的源/漏区的下部具有杂质扩散区。该方法包括以大的倾斜角执行离子注入操作，这增加了源极/漏极区的结深度，并且防止位于隔离区边缘处的金属硅化物太靠近源极/漏极结并导致不必要的电流泄漏。隔离区域被过蚀刻，其暴露源极/漏极区域的表面。因此，可以在暴露的源极/漏极表面上形成金属硅化物层，导致形成宽边界接触窗的更多的表面积，从而导致接触电阻和薄层电阻的降低。

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