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1. 发明授权

US06174791B1 Method for a pre-amorphization 失效
标题翻译：前非晶化方法
公开(公告)号：US06174791B1
公开(公告)日：2001-01-16
申请号：US09276294
申请日：1999-03-25
申请人： Tony Lin , Jih-Wen Chou , C. C. Hsue
发明人： Tony Lin , Jih-Wen Chou , C. C. Hsue
IPC分类号： H01L21425
CPC分类号： H01L21/28518 , H01L21/26506 , H01L29/665
摘要： A method for forming an amorphous silicon layer over the terminals of a MOS transistor. The method includes the steps of forming a mask layer having an opening that exposes the gate polysilicon layer over the MOS transistor. Next, using the mask layer as a mask, an inactive ion implant operation is carried out such that inactive ions are implanted into the gate polysilicon layer. Thereafter, again using the mask layer as a mask, a first heavy bombarding operation is carried out, implanting ions locally. Finally, the mask layer is removed and then a second heavy bombarding operation is carried out, implanting ions globally.
摘要翻译：一种用于在MOS晶体管的端子上形成非晶硅层的方法。该方法包括以下步骤：形成具有在MOS晶体管上暴露栅极多晶硅层的开口的掩模层。接下来，使用掩模层作为掩模，执行非活性离子注入操作，使得非活性离子注入到栅极多晶硅层中。此后，再次使用掩模层作为掩模，进行第一次重轰击操作，局部注入离子。最后，去除掩模层，然后进行第二次重轰击操作，全局注入离子。

2. 发明授权

US06211027B1 Method for manufacturing PMOS transistor 失效
标题翻译：制造PMOS晶体管的方法
公开(公告)号：US06211027B1
公开(公告)日：2001-04-03
申请号：US09444278
申请日：1999-11-19
申请人： Tony Lin , C. C. Hsue
发明人： Tony Lin , C. C. Hsue
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/266 , H01L29/1083 , H01L29/665 , H01L29/6653 , H01L29/6659
摘要： A method for manufacturing a PMOS transistor. A gate terminal is formed over a substrate. Spacers are formed on the sidewalls of the gate terminal. A source/drain terminal is formed in the substrate on each side of the gate terminal, and then a metal silicide layer is formed over the top surface of the gate terminal and the substrate. The spacers are next removed. Using the metal silicide layer as a mask, a source/drain extension region is formed in the substrate between the gate terminal and the source/drain terminal. Similarly, using the metal silicide layer as a mask, an anti-punchthrough region is form in the substrate interior under the source/drain extension region.
摘要翻译：一种用于制造PMOS晶体管的方法。栅极端子形成在基板上。隔板形成在栅极端子的侧壁上。源极/漏极端子形成在栅极端子的每一侧上的衬底中，然后在栅极端子和衬底的顶表面上形成金属硅化物层。接下来移除间隔物。使用金属硅化物层作为掩模，在栅极端子和源极/漏极端子之间的衬底中形成源极/漏极延伸区域。类似地，使用金属硅化物层作为掩模，在源极/漏极延伸区域下方的衬底内部形成抗穿透区域。

3. 发明申请

US20070259503A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070259503A1
公开(公告)日：2007-11-08
申请号：US11777291
申请日：2007-07-13
申请人： Hui-Chen Chang , Tony Lin , Brook Hsu , Cyrus LW Chen , Meng-Lin Lee , Wei-Tsun Shiau
发明人： Hui-Chen Chang , Tony Lin , Brook Hsu , Cyrus LW Chen , Meng-Lin Lee , Wei-Tsun Shiau
IPC分类号： H01L21/336
CPC分类号： H01L21/28114 , H01L21/31116 , H01L21/32137 , H01L21/823807 , H01L21/823864 , H01L29/42376 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： A method of fabricating a semiconductor device is provided herein. The semiconductor device includes a substrate, a gate dielectric layer, a gate, a pair of source/drain regions and a stressed layer. The gate dielectric layer is disposed on the substrate and the gate whose top area is larger than its bottom area is disposed on the gate dielectric layer. The source/drain regions are disposed in the substrate next to the sidewalls of the gate. The stressed layer is disposed on the substrate to cover the gate and the source/drain regions.
摘要翻译：本发明提供一种制造半导体器件的方法。半导体器件包括衬底，栅介质层，栅极，一对源/漏区和应力层。栅极电介质层设置在基板上，并且顶部区域大于其底部区域的栅极设置在栅极介电层上。源极/漏极区域设置在邻近栅极的侧壁的衬底中。应力层设置在基板上以覆盖栅极和源极/漏极区域。

4. 发明申请

US20060047811A1 Method and system of providing access to various data associated with a project 审中-公开
标题翻译：提供对与项目相关的各种数据的访问的方法和系统
公开(公告)号：US20060047811A1
公开(公告)日：2006-03-02
申请号：US10932569
申请日：2004-09-01
申请人： Daniel Lau , Daniel Crevier , Jorge Morinigo , Robert Vreeland , Shengyong Li , Stuart DeSpain , Brooke Nelson , Jeffrey Smith , James Grandy , Laura Neumann , Tony Lin , Vianna Tam
发明人： Daniel Lau , Daniel Crevier , Jorge Morinigo , Robert Vreeland , Shengyong Li , Stuart DeSpain , Brooke Nelson , Jeffrey Smith , James Grandy , Laura Neumann , Tony Lin , Vianna Tam
IPC分类号： G06F15/173
CPC分类号： H04L67/2852 , H04L51/16
摘要： Described is a system and method that enables project management across application programs, including an email program, calendar program, spreadsheet program, word processing program, note taking program and others. A central project-related view provides access to project-related data items and may display a schedule, a task list of tasks filtered as being relevant to a project, a note page related to a project, and emails relevant to the project. In addition, other application objects (file, documents, presentations and spreadsheets) are also captured in the view and presented for easy access. Metadata including a project identifier is maintained in a database for the various data items, allowing rapid location of the data items related to a project via query techniques. A project palette allows access to the items from within another application program, and a project gallery allows a user alternative access to the files related to a project.
摘要翻译：描述了一种能够跨应用程序进行项目管理的系统和方法，包括电子邮件程序，日历程序，电子表格程序，文字处理程序，记录程序等。中央项目相关视图提供对项目相关数据项的访问，并且可以显示计划，过滤为与项目相关的任务的任务列表，与项目相关的注释页面以及与项目相关的电子邮件。此外，其他应用对象（文件，文档，演示文稿和电子表格）也被捕获在视图中并被呈现以便于访问。包含项目标识符的元数据被保存在用于各种数据项的数据库中，允许通过查询技术快速定位与项目相关的数据项。项目调色板允许访问另一个应用程序中的项目，项目库允许用户对与项目相关的文件进行替代访问。

5. 发明申请

US20050110787A1 Display apparatus with power saving capability 有权
标题翻译：具有省电功能的显示装置
公开(公告)号：US20050110787A1
公开(公告)日：2005-05-26
申请号：US10720432
申请日：2003-11-24
申请人： Tony Lin
发明人： Tony Lin
IPC分类号： G09G3/00 , G09G5/00 , H02J9/00
CPC分类号： H02J9/005 , G09G3/00 , G09G2330/02 , G09G2330/021
摘要： A power control unit of a display apparatus includes an AC-to-DC converter for receiving an external AC power. A regulator receives a DC output from the converter, and is operable in one of an enabled state of outputting a target DC power when receiving a first level signal, and a disabled state of not outputting the target DC power when receiving a second level signal. An electronic switch is operable for switching from an OFF-mode, where a processor permits a delay circuit to output the second level signal to the regulator, to an ON-mode, where the electronic switch initially enables the delay circuit to output the first level signal to the regulator such that the processor receives the target DC power from the regulator and where the electronic switch outputs a trigger signal to the processor so as to enable the processor to latch the first level signal and to provide the target DC power to a display module.
摘要翻译：显示装置的电源控制单元包括用于接收外部AC电力的AC-DC转换器。调节器从转换器接收DC输出，并且在接收到第一电平信号时可以在输出目标DC电力的使能状态中的一个中工作，以及当接收到第二电平信号时不输出目标DC电力的禁止状态。电子开关可操作用于从处于允许延迟电路将第二电平信号输出到调节器的OFF模式切换到ON模式，其中电子开关最初使能延迟电路输出第一电平信号到调节器，使得处理器从调节器接收目标DC电力，并且其中电子开关向处理器输出触发信号，以使得处理器能够锁存第一电平信号并向显示器提供目标DC电力模块。

6. 发明授权

US06605005B1 Detachable laser pointer for golf putter 失效
标题翻译：高尔夫推杆可拆卸激光笔
公开(公告)号：US06605005B1
公开(公告)日：2003-08-12
申请号：US10198084
申请日：2002-07-19
申请人： Tony Lin
发明人： Tony Lin
IPC分类号： A63B6936
CPC分类号： A63B69/3614 , A63B69/3632 , A63B69/3676 , A63B69/3685 , A63B2071/0694
摘要： A detachable laser pointer is constructed to include a mounting base, the mounting base having a smoothly arched rear coupling groove for coupling to the shaft of a golf putter and a locating plate of C-shaped cross section upwardly extended from the smoothly arched coupling groove for plugging in between the shaft and grip of the golf putter and a front receiving groove, a joint rotatably coupled to the receiving groove, a laser module pivoted to the joint and adapted for emitting a laser beam to aim the putter head of the golf putter to the hole.
摘要翻译：可拆卸的激光指示器被构造成包括安装基座，该安装基座具有平滑拱形的后连接槽，用于联接到高尔夫推杆的轴上，以及从平滑的拱形联接槽向上延伸的C形横截面的定位板，用于插入高尔夫推杆的轴和把手之间以及前接收槽，可旋转地联接到接收槽的接头，激光模块，其枢转到接头并适于发射激光束以使高尔夫推杆的推杆头对准那个洞。

7. 发明授权

US06190981B1 Method for fabricating metal oxide semiconductor 有权
标题翻译：金属氧化物半导体的制造方法
公开(公告)号：US06190981B1
公开(公告)日：2001-02-20
申请号：US09243740
申请日：1999-02-03
申请人： Tony Lin , Jih-Wen Chou
发明人： Tony Lin , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L29/4983 , H01L29/4991 , H01L29/665
摘要： A method of for fabrication a metal oxide semiconductor transistor is described. A substrate with an isolation structure thereon is provided. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. The polysilicon layer is patterned to form a gate on the gate oxide layer. An offset spacer is formed on the sidewall of the gate. A source/drain extension is formed in the substrate on two sides of the gate by ion implantation. An insulating spacer is formed on the sidewall of the offset spacer. A source/drain region is formed in the substrate by ion implantation using the gate, the offset spacer and the insulating spacer as a mask. Salicide is formed on the gate and on the surface of the source/drain region. After forming the salicide, the offset spacer is removed. After removing the offset spacer, a halo doped region is formed in the substrate below the source/drain extension by ion implantation.
摘要翻译：描述了制造金属氧化物半导体晶体管的方法。提供其上具有隔离结构的基板。在衬底上形成栅氧化层。在栅氧化层上形成多晶硅层。图案化多晶硅层以在栅极氧化物层上形成栅极。在门的侧壁上形成偏移间隔物。通过离子注入在栅极两侧的衬底中形成源极/漏极延伸。绝缘间隔件形成在偏移间隔件的侧壁上。通过使用栅极，偏移间隔物和绝缘间隔物作为掩模的离子注入在衬底中形成源极/漏极区。在栅极和源极/漏极区域的表面上形成硅化物。在形成自对准硅胶后，去除偏移间隔物。在去除偏移间隔物之后，通过离子注入在源极/漏极延伸部下方的衬底中形成光晕掺杂区域。

8. 发明授权

US06171939B2 Method for forming polysilicon gate electrode 有权
标题翻译：多晶硅栅电极形成方法
公开(公告)号：US06171939B2
公开(公告)日：2001-01-09
申请号：US09348389
申请日：1999-07-07
申请人： Tony Lin
发明人： Tony Lin
IPC分类号： H01L213205
CPC分类号： H01L21/28052 , H01L29/4925 , H01L29/4933 , H01L29/665
摘要： A method for forming a polysilicon gate electrode. A semiconductor is provided. A gate oxide layer, a partially doped polysilicon layer and an undoped polysilicon are sequentially formed over the semiconductor substrate. The undoped polysilicon layer, the partially doped polysilicon layer and the gate oxide layer are patterned to form a gate electrode.
摘要翻译：一种形成多晶硅栅电极的方法。提供半导体。在半导体衬底上依次形成栅氧化层，部分掺杂多晶硅层和未掺杂多晶硅。对未掺杂的多晶硅层，部分掺杂的多晶硅层和栅极氧化物层进行构图以形成栅电极。

9. 发明授权

US6117743A Method of manufacturing MOS device using anti reflective coating 失效
标题翻译：使用抗反射涂层制造MOS器件的方法
公开(公告)号：US6117743A
公开(公告)日：2000-09-12
申请号：US203023
申请日：1998-12-01
申请人： Wen-Kuan Yeh , Tony Lin , Coming Chen
发明人： Wen-Kuan Yeh , Tony Lin , Coming Chen
IPC分类号： H01L21/027 , H01L21/28 , H01L21/336 , H01L29/49
CPC分类号： H01L29/66575 , H01L21/0276 , H01L21/28061 , H01L21/28123 , H01L29/4941 , H01L29/66545 , Y10S438/952
摘要： A method of manufacturing MOS device including the steps of providing a semiconductor substrate that has a device isolation structure thereon, and then depositing a gate oxide layer, a polysilicon layer and an anti-reflection coating in sequence over the substrate. Next, a gate structure is patterned out of the gate oxide layer, the polysilicon layer and the anti-reflection coating. Then, spacers are formed on the sidewalls of the gate structure. Thereafter, a metal silicide layer is formed over source/drain regions. After that, an inter-layer dielectric (ILD) layer is formed over the gate structure and the entire substrate. Then, the inter-layer dielectric layer is planarized to expose the anti-reflection coating. Next, the anti-reflection coating is removed, and then a barrier layer is deposited over the inter-layer dielectric layer and the polysilicon layer. Subsequently, a conductive layer is deposited over the barrier layer. Finally, a chemical-mechanical polishing operation is carried out to planarize the conductive layer, retaining only the conductive layer above the polysilicon layer.
摘要翻译：一种制造MOS器件的方法，包括以下步骤：提供在其上具有器件隔离结构的半导体衬底，然后在衬底上依次沉积栅极氧化物层，多晶硅层和抗反射涂层。接下来，栅极结构从栅极氧化物层，多晶硅层和抗反射涂层构图。然后，在栅极结构的侧壁上形成间隔物。此后，在源极/漏极区域上形成金属硅化物层。之后，在栅极结构和整个衬底上形成层间介电层（ILD）层。然后，层间电介质层被平坦化以暴露抗反射涂层。接下来，去除防反射涂层，然后在层间电介质层和多晶硅层上沉积阻挡层。随后，在阻挡层上沉积导电层。最后，进行化学机械抛光操作以使导电层平坦化，仅在多晶硅层上保留导电层。

10. 发明授权

US6025241A Method of fabricating semiconductor devices with self-aligned silicide 失效
标题翻译：制造具有自对准硅化物的半导体器件的方法
公开(公告)号：US6025241A
公开(公告)日：2000-02-15
申请号：US73576
申请日：1998-05-06
申请人： Tony Lin , Water Lur
发明人： Tony Lin , Water Lur
IPC分类号： H01L21/3115 , H01L21/336 , H01L21/28
CPC分类号： H01L29/66507 , H01L29/6659 , H01L21/31155 , Y10S148/147
摘要： A method for fabricating a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor, with self-aligned silicide is provided. This method can prevent junction leakage between the silicide and the substrate so as to allow the resultant semiconductor device to have reliable performance. The method includes the steps of preparing a semiconductor substrate; forming at least one transistor element over the substrate, the transistor element including a pair of source/drain regions, a gate, a dielectric layer over the gate, and a spacer on the sidewall of the gate; and performing an ion-bombardment process so as to transport one part of the dielectric layer that is adjacent to the top of the spacer to beside the bottom of the spacer. Through this method, the resultant semiconductor device is reliable in operation since the drawback of the occurrence of leakage current or short-circuit that could be otherwise resulted between the self-aligned silicide and the substrate owing to the short-channel effect can be eliminated. Moreover, the resultant semiconductor device has increased anti-static capability that can protect the semiconductor device against electro-static damage.
摘要翻译：提供了一种用于制造具有自对准硅化物的半导体器件（例如MOS（金属氧化物半导体）晶体管）的方法。该方法可以防止硅化物与衬底之间的结漏电，从而使所得的半导体器件具有可靠的性能。该方法包括制备半导体衬底的步骤; 在所述衬底上形成至少一个晶体管元件，所述晶体管元件包括一对源极/漏极区域，栅极，所述栅极上的电介质层以及所述栅极侧壁上的间隔物; 并且进行离子轰击处理，以将邻近间隔物顶部的电介质层的一部分输送到间隔物的底部旁边。通过该方法，由于短沟道效应，可以消除由于短路导致的自对准硅化物和衬底之间的漏电流或短路的缺点，所以得到的半导体器件工作可靠。此外，所得到的半导体器件具有增强的抗静电能力，可以保护半导体器件免受静电损坏。

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