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1. 发明授权

US07969760B2 Semiconductor memory device and manufacturing method of the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07969760B2
公开(公告)日：2011-06-28
申请号：US11790590
申请日：2007-04-26
申请人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
发明人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
IPC分类号： G11C5/06
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.
摘要翻译：本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。在选择晶体管的栅电极上形成两条选择线。一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。也就是说，在选择线和栅电极之间形成绝缘膜。如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。选择线被构造成连接到另一个选择晶体管。

2. 发明申请

US20070285983A1 Semiconductor memory device and manufacturing method of the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070285983A1
公开(公告)日：2007-12-13
申请号：US11790590
申请日：2007-04-26
申请人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
发明人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
IPC分类号： G11C11/34 , H01L21/336
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.
摘要翻译：本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。在选择晶体管的栅电极上形成两条选择线。一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。也就是说，在选择线和栅电极之间形成绝缘膜。如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。选择线被构造成连接到另一个选择晶体管。

3. 发明申请

US20110235386A1 Semiconductor Memory Device and Manufacturing Method of the Same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110235386A1
公开(公告)日：2011-09-29
申请号：US13154113
申请日：2011-06-06
申请人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
发明人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
IPC分类号： G11C5/02
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.
摘要翻译：本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。在选择晶体管的栅电极上形成两条选择线。一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。也就是说，在选择线和栅电极之间形成绝缘膜。如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。选择线被构造成连接到另一个选择晶体管。

4. 发明申请

US20070228455A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070228455A1
公开(公告)日：2007-10-04
申请号：US11619561
申请日：2007-01-03
申请人： Yoshitaka Sasago , Tomoyuki Ishii , Toshiyuki Mine
发明人： Yoshitaka Sasago , Tomoyuki Ishii , Toshiyuki Mine
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： In the memory array area of a semiconductor substrate, memory cells of a NAND flash memory are arranged in a matrix in the row direction and the column direction. A plurality of memory cells arranged in the row direction are mutually isolated by device isolation trenches having a thin strip planar shape extending in the column direction. The diameter of the device isolation trenches in the row direction at the bottom portion thereof is larger than that near the surface.
摘要翻译：在半导体衬底的存储器阵列区域中，NAND闪速存储器的存储单元被排列成行方向和列方向的矩阵。沿行方向布置的多个存储单元通过在列方向上延伸的薄的带状平面形状的器件隔离沟相互隔离。器件隔离沟槽在其底部的行方向上的直径大于靠近表面的直径。

5. 发明申请

US20050173751A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20050173751A1
公开(公告)日：2005-08-11
申请号：US11002800
申请日：2004-12-03
申请人： Tomoyuki Ishii , Toshiyuki Mine , Yoshitaka Sasago , Taro Osabe
发明人： Tomoyuki Ishii , Toshiyuki Mine , Yoshitaka Sasago , Taro Osabe
IPC分类号： G11C11/34 , G11C16/04 , H01L21/8239 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0475 , G11C16/0491 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory device that uses inversion layers formed on a surface of its semiconductor substrate as data lines, which is capable of satisfying the requirements of suppressing both characteristic variation among memory cells and bit cost. In order to achieve the above object, in the memory device, a plurality of assist gates are formed so as to be embedded in a p-type well via a silicon oxide film, respectively and silicon nanocrystal grains of about 6 nm in average diameter used for storing information are formed without being in contact with one another. Then, a plurality of word lines are formed practically in a direction vertically to the assist gates and the space between adjacent those of the plurality of word lines is set under ½ of the width (gate length) of the word lines. Consequently, the inversion layers formed at side faces of the assist gates will be used as local data lines, thereby the resistance is lowered and the writing characteristic variation among memory cells in a memory mat is suppressed.
摘要翻译：使用形成在其半导体衬底的表面上的反型层作为数据线的非易失性半导体存储器件，其能够满足抑制存储器单元之间的特性变化和位成本的要求。为了实现上述目的，在存储装置中，分别形成多个辅助栅极，以分别通过氧化硅膜嵌入p型阱中，并使用平均直径约6nm的硅纳米晶粒用于存储信息的形成而不彼此接触。然后，在垂直于辅助栅极的方向上形成多个字线，并且将多个字线的相邻字线之间的空间设置在字线的宽度（栅极长度）的1/2以下。因此，形成在辅助栅极的侧面的反转层将被用作本地数据线，从而电阻降低，并且抑制存储器垫中的存储单元之间的写入特性变化。

6. 发明申请

US20070109870A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20070109870A1
公开(公告)日：2007-05-17
申请号：US11652023
申请日：2007-01-11
申请人： Hideaki Kurata , Kazuo Otsuga , Yoshitaka Sasago , Takashi Kobayashi , Tsuyoshi Arigane
发明人： Hideaki Kurata , Kazuo Otsuga , Yoshitaka Sasago , Takashi Kobayashi , Tsuyoshi Arigane
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L27/11524
摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.
摘要翻译：在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像编程特性恶化，电流消耗增加，读取失败。为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在上述辅助电极不导电。

7. 发明授权

US07184318B2 Semiconductor memory device 有权
公开(公告)号：US07184318B2
公开(公告)日：2007-02-27
申请号：US11197485
申请日：2005-08-05
申请人： Hideaki Kurata , Kazuo Otsuga , Yoshitaka Sasago , Takashi Kobayashi , Tsuyoshi Arigane
发明人： Hideaki Kurata , Kazuo Otsuga , Yoshitaka Sasago , Takashi Kobayashi , Tsuyoshi Arigane
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L27/11524
摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.

8. 发明申请

US20120211718A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120211718A1
公开(公告)日：2012-08-23
申请号：US13440225
申请日：2012-04-05
申请人： AKIO SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： AKIO SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： H01L45/00
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

9. 发明授权

US07471563B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07471563B2
公开(公告)日：2008-12-30
申请号：US11652023
申请日：2007-01-11
申请人： Hideaki Kurata , Kazuo Otsuga , Yoshitaka Sasago , Takashi Kobayashi , Tsuyoshi Arigane
发明人： Hideaki Kurata , Kazuo Otsuga , Yoshitaka Sasago , Takashi Kobayashi , Tsuyoshi Arigane
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L27/11524
摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.
摘要翻译：在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像编程特性恶化，电流消耗增加，读取失败。为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在上述辅助电极不导电。

10. 发明授权

US08427865B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08427865B2
公开(公告)日：2013-04-23
申请号：US13440225
申请日：2012-04-05
申请人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： G11C11/00 , H01L29/80
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

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