会员体验
专利管家（专利管理）
工作空间（专利管理）
风险监控（情报监控）
数据分析（专利分析）
侵权分析（诉讼无效）
联系我们
交流群
官方交流：
QQ群： 891211   
微信请扫码    >>>
现在联系顾问~
下载
著录项
PDF全文
热词
    • 1. 发明授权
      US07449747B2 Semiconductor memory device 失效
    • Semiconductor memory device
    • 半导体存储器件
    • US07449747B2
    • 2008-11-11
    • US11311162
    • 2005-12-20
    • Tomoyuki Ishii , Kazunori Furusawa , Hideaki Kurata , Yoshihiro Ikeda
    • Tomoyuki Ishii , Kazunori Furusawa , Hideaki Kurata , Yoshihiro Ikeda
    • H01L29/788
    • H01L27/11521 , B82Y10/00 , G11C11/5621 , G11C16/0458 , G11C2211/5612 , G11C2216/06 , H01L27/115 , H01L29/42332 , H01L29/7887
    • Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for multiple-value memory with multiple-level threshold values can be made small in area if the inversion layer is utilized as the wiring; however, it suffers the disadvantage of greatly varying in writing characteristics from cell to cell. Another promising method of realizing multiple-value memory is to change the storage locations. This method, however, poses a problem with disturbance at the time of operation. The present invention provides one way to realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics. The semiconductor memory has a source region and a drain region, which are formed parallel to each other, and an assist electrode which is between and parallel to the source and drain regions without overlapping, so that it uses, at the time of writing, the assist electrode as the assist electrode for hot electrons to be injected at the source side and it uses, at the time of reading, the inversion layer formed under the assist electrode as the source region or the drain region.
    • 闪存正在迅速降价。 需要一种允许大小缩小并适合多值内存的新内存系统。 如果使用反转层作为布线，则可以使适用于具有多级阈值的多值存储器的AND型闪速存储器的面积小; 然而，它具有从细胞到细胞的书写特征大大变化的缺点。 实现多值存储器的另一个有希望的方法是改变存储位置。 然而，这种方法在操作时存在干扰问题。 本发明提供了实现具有减小的写入特性的单元到单元变化的半导体存储器件的一种方式。 半导体存储器具有彼此平行形成的源极区域和漏极区域以及辅助电极，其在源极和漏极区域之间并且平行于其而不重叠，从而在写入时使用辅助电极 辅助电极作为用于在源极侧注入的热电子的辅助电极，并且在读取时使用形成在辅助电极下方的反型层作为源极区域或漏极区域。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明申请
      US20060097311A1 Semiconductor memory device 失效
    • Semiconductor memory device
    • 半导体存储器件
    • US20060097311A1
    • 2006-05-11
    • US11311162
    • 2005-12-20
    • Tomoyuki Ishii , Kazunori Furusawa , Hideaki Kurata , Yoshihiro Ikeda
    • Tomoyuki Ishii , Kazunori Furusawa , Hideaki Kurata , Yoshihiro Ikeda
    • H01L29/788
    • H01L27/11521 , B82Y10/00 , G11C11/5621 , G11C16/0458 , G11C2211/5612 , G11C2216/06 , H01L27/115 , H01L29/42332 , H01L29/7887
    • Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for multiple-value memory with multiple-level threshold values can be made small in area if the inversion layer is utilized as the wiring; however, it suffers the disadvantage of greatly varying in writing characteristics from cell to cell. Another promising method of realizing multiple-value memory is to change the storage locations. This method, however, poses a problem with disturbance at the time of operation. The present invention provides one way to realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics. The semiconductor memory has a source region and a drain region, which are formed parallel to each other, and an assist electrode which is between and parallel to the source and drain regions without overlapping, so that it uses, at the time of writing, the assist electrode as the assist electrode for hot electrons to be injected at the source side and it uses, at the time of reading, the inversion layer formed under the assist electrode as the source region or the drain region.
    • 闪存正在迅速降价。 需要一种允许大小缩小并适合多值内存的新内存系统。 如果使用反转层作为布线，则可以使适用于具有多级阈值的多值存储器的AND型闪速存储器的面积小; 然而，它具有从细胞到细胞的书写特征大大变化的缺点。 实现多值存储器的另一个有希望的方法是改变存储位置。 然而，这种方法在操作时存在干扰问题。 本发明提供了实现具有减小的写入特性的单元到单元变化的半导体存储器件的一种方式。 半导体存储器具有彼此平行形成的源极区域和漏极区域以及辅助电极，其在源极和漏极区域之间并且平行于其而不重叠，从而在写入时使用辅助电极 辅助电极作为用于在源极侧注入的热电子的辅助电极，并且在读取时使用形成在辅助电极下方的反型层作为源极区域或漏极区域。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US5598368A Batch erasable nonvolatile memory device and erasing method 失效
    • Batch erasable nonvolatile memory device and erasing method
    • 批量可擦除非易失性存储器件和擦除方法
    • US5598368A
    • 1997-01-28
    • US445105
    • 1995-05-19
    • Masahito Takahashi , Michiko Odagiri , Takeshi Furuno , Kazunori Furusawa , Masashi Wada
    • Masahito Takahashi , Michiko Odagiri , Takeshi Furuno , Kazunori Furusawa , Masashi Wada
    • G11C17/00 , G11C16/02 , G11C16/16 , G11C16/34 , G11C13/00
    • G11C16/3477 , G11C16/16 , G11C16/3409 , G11C16/3445 , G11C16/3468
    • A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by a ejecting an electric charge accumulated at floating gates by program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltage, or is provided with an automatic erasing circuit for executing these operations.
    • 批量可擦除非易失性存储装置和使用该存储器单元的装置，该存储单元适于通过通过编程操作（包括预写操作）弹出在浮动栅极上累积的电荷来执行擦除操作， 序列，用于读取擦除单元的存储单元并且在不存储电荷的浮动栅极上对那些非易失性存储单元执行预写操作的第一操作，用于在存储单元中执行批量擦除操作的第二操作 在相对较大的擦除参考电压下具有相对大的能量的所述擦除单元的非易失性存储单元的高速度，用于执行所有擦除的非易失性存储单元的读操作的第三操作和对那些非易失性存储单元的写操作 适于具有相对低的阈值电压，以及第四操作，用于以低速执行批量擦除操作 所述擦除单元的非易失性存储单元在相对小的擦除参考电压下具有相对小的能量，或者设置有用于执行这些操作的自动擦除电路。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
每页展示10个专利
每页展示10个专利
每页展示20个专利
每页展示50个专利
每页展示100个专利

IPRDB

最新中国发明专利 最新美国发明专利 技术领域 专利库 专利分类库 国际专利分类库

热门服务

会员版试用 API 数据接口 找代理 知嘟嘟专利交易 排行榜 大学排行榜 专利百科

关于我们

平台介绍 战略合作 网站地图

友情链接

知嘟嘟专利交易 国家知识产权局 中国商标网

联系方式


©2019-2023 上海吉码数字技术有限公司 版权所有，并保留所有权利 沪ICP备20016256号-6 沪公网安备31011702005475号