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1. 发明申请

US20080046643A1 Memory card 失效
标题翻译：存储卡
公开(公告)号：US20080046643A1
公开(公告)日：2008-02-21
申请号：US11907422
申请日：2007-10-12
申请人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
发明人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
IPC分类号： G06F12/00
CPC分类号： G11C16/16 , G06F3/0614 , G06F3/0626 , G06F3/0656 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G11C16/0416
摘要： A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.
摘要翻译：存储卡（1）包括电可重写非易失性存储器（4），具有执行指令的功能的数据处理器（3），以及管理非易失性存储器中文件数据的分配，接口控制电路 2）具有建立外部接口的功能，用于响应于外部命令控制数据处理器执行指令并且用于控制对非易失性存储器的访问以及用于临时存储文件数据的缓冲存储器（7）。接口控制电路包括用于对外部提供的第一命令进行解码并指示数据处理器从缓冲存储器获取指令并进行操作的命令控制装置。

2. 发明授权

US07002853B2 Memory card having a buffer memory for storing testing instruction 失效
标题翻译：具有用于存储测试指令的缓冲存储器的存储卡
公开(公告)号：US07002853B2
公开(公告)日：2006-02-21
申请号：US10874381
申请日：2004-06-24
申请人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
发明人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G06F3/0614 , G06F3/0626 , G06F3/0656 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G11C16/0416
摘要： A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.
摘要翻译：存储卡（1）包括电可重写非易失性存储器（4），具有执行指令的功能的数据处理器（3），以及管理非易失性存储器中文件数据的分配，接口控制电路 2）具有建立外部接口的功能，用于响应于外部命令控制数据处理器执行指令并且用于控制对非易失性存储器的访问以及用于临时存储文件数据的缓冲存储器（7）。接口控制电路包括用于对外部提供的第一命令进行解码并指示数据处理器从缓冲存储器获取指令并进行操作的命令控制装置。

3. 发明授权

US06643725B1 Memory card having a buffer memory for storing testing instruction 有权
标题翻译：具有用于存储测试指令的缓冲存储器的存储卡
公开(公告)号：US06643725B1
公开(公告)日：2003-11-04
申请号：US09495955
申请日：2000-02-02
申请人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
发明人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
IPC分类号： G06F1300
CPC分类号： G11C16/16 , G06F3/0614 , G06F3/0626 , G06F3/0656 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G11C16/0416
摘要： A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.
摘要翻译：存储卡（1）包括电可重写非易失性存储器（4），具有执行指令并管理非易失性存储器中的文件数据分配的功能的数据处理器（3），接口控制电路）具有建立外部接口的功能，用于响应于外部命令控制数据处理器执行指令并且用于控制对非易失性存储器的访问以及用于临时存储文件数据的缓冲存储器（7）。接口控制电路包括用于对外部提供的第一命令进行解码并指示数据处理器从缓冲存储器获取指令并进行操作的命令控制装置。

4. 发明申请

US20050262292A1 Memory card 有权
标题翻译：存储卡
公开(公告)号：US20050262292A1
公开(公告)日：2005-11-24
申请号：US11182956
申请日：2005-07-18
申请人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
发明人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
IPC分类号： G06K19/07 , G06F3/06 , G06F12/00 , G06F12/06 , G06F13/00 , G11C16/04 , G11C16/16 , G11C29/00
CPC分类号： G11C16/16 , G06F3/0614 , G06F3/0626 , G06F3/0656 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G11C16/0416
摘要： A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.
摘要翻译：存储卡（1）包括电可重写非易失性存储器（4），具有执行指令的功能的数据处理器（3），以及管理非易失性存储器中文件数据的分配，接口控制电路 2）具有建立外部接口的功能，用于响应于外部命令控制数据处理器执行指令并且用于控制对非易失性存储器的访问以及用于临时存储文件数据的缓冲存储器（7）。接口控制电路包括用于对外部提供的第一命令进行解码并指示数据处理器从缓冲存储器获取指令并进行操作的命令控制装置。

5. 发明授权

US07440337B2 Nonvolatile semiconductor memory apparatus having buffer memory for storing a program and buffering work data 失效
标题翻译：具有用于存储程序和缓冲工作数据的缓冲存储器的非易失性半导体存储装置
公开(公告)号：US07440337B2
公开(公告)日：2008-10-21
申请号：US11907422
申请日：2007-10-12
申请人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
发明人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G06F3/0614 , G06F3/0626 , G06F3/0656 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G11C16/0416
摘要： A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.
摘要翻译：存储卡（1）包括电可重写非易失性存储器（4），具有执行指令的功能的数据处理器（3），以及管理非易失性存储器中文件数据的分配，接口控制电路 2）具有建立外部接口的功能，用于响应于外部命令控制数据处理器执行指令并且用于控制对非易失性存储器的访问以及用于临时存储文件数据的缓冲存储器（7）。接口控制电路包括用于对外部提供的第一命令进行解码并指示数据处理器从缓冲存储器获取指令并进行操作的命令控制装置。

6. 发明授权

US07292480B2 Memory card having buffer memory for storing testing instruction 有权
标题翻译：具有用于存储测试指令的缓冲存储器的存储卡
公开(公告)号：US07292480B2
公开(公告)日：2007-11-06
申请号：US11182956
申请日：2005-07-18
申请人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
发明人： Kenji Kozakai , Yuusuke Jono , Motoki Kanamori , Kazunori Furusawa , Atsushi Shikata , Yosuke Yukawa
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G06F3/0614 , G06F3/0626 , G06F3/0656 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G11C16/0416
摘要： A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.
摘要翻译：存储卡（1）包括电可重写非易失性存储器（4），具有执行指令的功能的数据处理器（3），以及管理非易失性存储器中文件数据的分配，接口控制电路 2）具有建立外部接口的功能，用于响应于外部命令控制数据处理器执行指令并且用于控制对非易失性存储器的访问以及用于临时存储文件数据的缓冲存储器（7）。接口控制电路包括用于对外部提供的第一命令进行解码并指示数据处理器从缓冲存储器获取指令并进行操作的命令控制装置。

7. 发明授权

US07116578B2 Non-volatile memory device and data storing method 有权
公开(公告)号：US07116578B2
公开(公告)日：2006-10-03
申请号：US10796995
申请日：2004-03-11
申请人： Motoki Kanamori , Takayuki Tamura , Kenji Kozakai , Atsushi Shikata , Shinsuke Asari
发明人： Motoki Kanamori , Takayuki Tamura , Kenji Kozakai , Atsushi Shikata , Shinsuke Asari
IPC分类号： G11C14/00 , G11C16/04 , G11C7/10 , G11C8/00 , G06F13/00
CPC分类号： G11C16/10 , G11C2207/229
摘要： In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.

8. 发明授权

US06731537B2 Non-volatile memory device and data storing method 有权
标题翻译：非易失性存储器件和数据存储方法
公开(公告)号：US06731537B2
公开(公告)日：2004-05-04
申请号：US10082310
申请日：2002-02-26
申请人： Motoki Kanamori , Takayuki Tamura , Kenji Kozakai , Atsushi Shikata , Shinsuke Asari
发明人： Motoki Kanamori , Takayuki Tamura , Kenji Kozakai , Atsushi Shikata , Shinsuke Asari
IPC分类号： G11C1400
CPC分类号： G11C16/10 , G11C2207/229
摘要： In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.
摘要翻译：在包含非易失性存储器和缓冲存储器的卡存储装置中，缓冲存储器包括多个存储体。数据从主机CPU顺序传送到缓冲存储器的存储区，数据从变为满的存储体传输到非易失性存储器，当要写入非易失性存储器的一个数据单元时，开始写入操作一次存储器已被转移，并且在不等待写入数据的情况下，下一个写入数据从主机CPU传送到从其传送写入数据的存储体。

9. 发明授权

US07933158B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07933158B2
公开(公告)日：2011-04-26
申请号：US12896016
申请日：2010-10-01
申请人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
发明人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
IPC分类号： G11C5/14
CPC分类号： G06F12/0246 , G06F11/1068 , G06F12/06 , G06F2212/1036 , G11C16/04 , G11C16/10 , G11C16/349 , G11C29/44 , G11C29/76 , G11C2029/0409
摘要： For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.
摘要翻译：对于允许电子写入和擦除要存储的信息（例如闪存）的非易失性存储器，系统开发者的负载将被减少，并且即使这样的系统的重要数据也可以避免由于管理和地址转换信息被破坏，系统无法运行的异常状态。非易失性存储器设置有替换功能，以替换包括不能正常写入或擦除的缺陷存储器单元的存储器单元组，所述存储器单元不包括不存在缺陷存储器单元的存储单元组，重写次数用于掌握数量的每个存储器单元组中的数据重写，并且因此执行存储单元组的替换，使得多个存储单元组之间的重写次数可能没有显着差异，以及用于检测和校正任何错误的错误校正功能存储在存储器阵列中的数据，其中从替换功能导出的第一地址转换信息和从重写平均函数导出的第二地址转换信息被存储在存储器阵列中的分别规定的区域中，并且第一地址转换信息和第二地址关于相同存储单元组的翻译信息是sto 以时间序列的多个集合中的红色。

10. 发明申请

US20080158963A1 NONVOLATILE MEMORY 有权
标题翻译：非易失性存储器
公开(公告)号：US20080158963A1
公开(公告)日：2008-07-03
申请号：US12048208
申请日：2008-03-13
申请人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
发明人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
IPC分类号： G11C16/04
CPC分类号： G06F12/0246 , G06F11/1068 , G06F12/06 , G06F2212/1036 , G11C16/04 , G11C16/10 , G11C16/349 , G11C29/44 , G11C29/76 , G11C2029/0409
摘要： For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.
摘要翻译：对于允许电子写入和擦除要存储的信息（例如闪存）的非易失性存储器，系统开发者的负载将被减少，并且即使这样的系统的重要数据也可以避免由于管理和地址转换信息被破坏，系统无法运行的异常状态。非易失性存储器设置有替换功能，以替换包括不能正常写入或擦除的缺陷存储器单元的存储器单元组，所述存储器单元不包括不存在缺陷存储器单元的存储单元组，重写次数用于掌握数量的每个存储器单元组中的数据重写，并且因此执行存储单元组的替换，使得多个存储单元组之间的重写次数可能没有显着差异，以及用于检测和校正任何错误的错误校正功能存储在存储器阵列中的数据，其中从替换功能导出的第一地址转换信息和从重写平均函数导出的第二地址转换信息被存储在存储器阵列中的分别规定的区域中，并且第一地址转换信息和第二地址关于相同存储单元组的翻译信息是sto 以时间序列的多个集合中的红色。

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