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    • 4. 发明授权
    • ADPLL circuit, semiconductor device, and portable information device
    • ADPLL电路,半导体器件和便携式信息器件
    • US08638142B2
    • 2014-01-28
    • US13616449
    • 2012-09-14
    • Ryo EndoJiro ShimboTomomitsu Kitamura
    • Ryo EndoJiro ShimboTomomitsu Kitamura
    • H03L7/06
    • H03L7/113H03L7/099H03L7/103H03L2207/06H03L2207/50
    • The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.
    • 本发明提供了在ADPLL环境或靠近ADPLL环境的环境下的ABS精度改进手段,实现了ABS的加工时间缩短。 在ABS电路中的数字频率比较器中,准备用于存储从DPFD输出的DPE信号中的初始相位差的DFF。 在ABS操作开始之后,从DPFD输出的DPE信号被记录为将DPFD的内部电路中的初始相位差表示为DFF的信号。 之后,数字频率比较器通过使用从输入DPE信号中减去记录在DFF中的初始相位误差获得的信号来执行ABS,从而实现高速和稳定的ABS操作。
    • 5. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT
    • 半导体集成电路
    • US20100052795A1
    • 2010-03-04
    • US12540248
    • 2009-08-12
    • Takahiro NakamuraTomomitsu KitamuraTaizo YamawakiTakayasu NorimatsuToshiya Uozumi
    • Takahiro NakamuraTomomitsu KitamuraTaizo YamawakiTakayasu NorimatsuToshiya Uozumi
    • H03L7/099
    • H03J3/20H03B5/1215H03B5/1228H03B5/1243H03B5/1265H03B5/1293H03J2200/10
    • The present invention provides a semiconductor integrated circuit capable of reducing a chip occupied area and reducing variations in control gain of a digitally controlled oscillator. The semiconductor integrated circuit is equipped with the digitally controlled oscillator. The digitally controlled oscillator comprises oscillation transistors and a resonant circuit. The resonant circuit comprises inductances, a frequency coarse-tuning variable capacitor array and a frequency fine-tuning variable capacitor array. The frequency coarse-tuning variable capacitor array comprises a plurality of coarse-tuning capacitor unit cells. The frequency fine-tuning variable capacitor array comprises a plurality of fine-tuning capacitor unit cells. The capacitance values of the coarse-tuning capacitor unit cells of the frequency coarse-tuning variable capacitor array are set in accordance with a binary weight 2M−1. The capacitance values of the fine-tuning capacitor unit cells of the frequency fine-tuning variable capacitor array are also set in accordance with a binary weight 2N−1.
    • 本发明提供一种能够减少芯片占用面积并减少数字控制振荡器的控制增益的变化的半导体集成电路。 半导体集成电路配有数字控制振荡器。 数字控制振荡器包括振荡晶体管和谐振电路。 谐振电路包括电感,频率粗调可变电容器阵列和频率微调可变电容器阵列。 频率粗调可变电容器阵列包括多个粗调谐电容器单元。 频率微调可变电容器阵列包括多个微调电容器单元。 频率粗调可变电容器阵列的粗​​调电容器单元的电容值根据二进制权重2M-1来设定。 频率微调可变电容器阵列的微调电容器单元的电容值也根据二进制权重2N-1设定。
    • 7. 发明授权
    • ADPLL circuit, semiconductor device, and portable information device
    • ADPLL电路,半导体器件和便携式信息器件
    • US08299828B2
    • 2012-10-30
    • US13463982
    • 2012-05-04
    • Ryo EndoJiro ShimboTomomitsu Kitamura
    • Ryo EndoJiro ShimboTomomitsu Kitamura
    • H03L7/06
    • H03L7/113H03L7/099H03L7/103H03L2207/06H03L2207/50
    • The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.
    • 本发明提供了在ADPLL环境或靠近ADPLL环境的环境下的ABS精度改进手段,实现了ABS的加工时间缩短。 在ABS电路中的数字频率比较器中,准备用于存储从DPFD输出的DPE信号中的初始相位差的DFF。 在ABS操作开始之后,从DPFD输出的DPE信号被记录为将DPFD的内部电路中的初始相位差表示为DFF的信号。 之后,数字频率比较器通过使用从输入DPE信号中减去记录在DFF中的初始相位误差获得的信号来执行ABS,从而实现高速和稳定的ABS操作。