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1. 发明申请

US20120327305A1 VIDEO AUDIO PROCESSING DEVICE AND STANDBY AND RETURN METHOD THEREOF 审中-公开
标题翻译：视频音频处理设备及其备用和返回方法
公开(公告)号：US20120327305A1
公开(公告)日：2012-12-27
申请号：US13604855
申请日：2012-09-06
申请人： Tomokuni YAMAGUCHI , Norihiko Mizobata , Shirou Yoshioka
发明人： Tomokuni YAMAGUCHI , Norihiko Mizobata , Shirou Yoshioka
IPC分类号： H04N5/222
CPC分类号： H04N5/44 , H04N5/63 , H04N21/4436
摘要： In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.
摘要翻译：在视频音频处理装置中，信号处理块（11,12）包括指令存储器（111,121），并根据加载到指令存储器中的程序进行信号处理。主存储部分（20）具有自刷新功能，并且可从信号处理块访问。辅助存储部分（30）存储用于使信号处理块执行信号处理的程序。控制部（15）在接收到备用指示时，以从辅助存储部向主存储部传送程序的方式进行控制，在主存储部中设置自刷新，并且在接收到返回指令以取消主存储部中的自刷新的方式进行控制，将程序从主存储部加载到信号处理块中的指令存储器，并且激活信号处理块。

2. 发明授权

US08284323B2 Video audio processing device and standby and return method thereof 失效
标题翻译：视频音频处理装置及其待机和返回方法
公开(公告)号：US08284323B2
公开(公告)日：2012-10-09
申请号：US12440713
申请日：2008-07-08
申请人： Tomokuni Yamaguchi , Norihiko Mizobata , Shirou Yoshioka
发明人： Tomokuni Yamaguchi , Norihiko Mizobata , Shirou Yoshioka
IPC分类号： H04N7/01
CPC分类号： H04N5/44 , H04N5/63 , H04N21/4436
摘要： In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.
摘要翻译：在视频音频处理装置中，信号处理块（11,12）包括指令存储器（111,121），并根据加载到指令存储器中的程序进行信号处理。主存储部分（20）具有自刷新功能，并且可从信号处理块访问。辅助存储部分（30）存储用于使信号处理块执行信号处理的程序。控制部（15）在接收到备用指示时，以从辅助存储部向主存储部传送程序的方式进行控制，在主存储部中设置自刷新，并且在接收到返回指令以取消主存储部中的自刷新的方式进行控制，将程序从主存储部加载到信号处理块中的指令存储器，并且激活信号处理块。

3. 发明申请

US20100073573A1 VIDEO AUDIO PROCESSING DEVICE AND STANDBY AND RETURN METHOD THEREOF 失效
标题翻译：视频音频处理设备及其备用和返回方法
公开(公告)号：US20100073573A1
公开(公告)日：2010-03-25
申请号：US12440713
申请日：2008-07-08
申请人： Tomokuni Yamaguchi , Norihiko Mizobata , Shirou Yoshioka
发明人： Tomokuni Yamaguchi , Norihiko Mizobata , Shirou Yoshioka
IPC分类号： H04N9/64 , H04N5/44
CPC分类号： H04N5/44 , H04N5/63 , H04N21/4436
摘要： In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.
摘要翻译：在视频音频处理装置中，信号处理块（11,12）包括指令存储器（111,121），并根据加载到指令存储器中的程序进行信号处理。主存储部分（20）具有自刷新功能，并且可从信号处理块访问。辅助存储部分（30）存储用于使信号处理块执行信号处理的程序。控制部（15）在接收到备用指示时，以从辅助存储部向主存储部传送程序的方式进行控制，在主存储部中设置自刷新，并且在接收到返回指令以取消主存储部中的自刷新的方式进行控制，将程序从主存储部加载到信号处理块中的指令存储器，并且激活信号处理块。

4. 发明申请

US20090083530A1 Computer System, Data Structure Representing Configuration Information, Mapping System, and Mapping Method 审中-公开
标题翻译：计算机系统，表示配置信息的数据结构，映射系统和映射方法
公开(公告)号：US20090083530A1
公开(公告)日：2009-03-26
申请号：US11886868
申请日：2006-04-04
申请人： Osamu Nishijima , Shirou Yoshioka , Yukihiro Sasagawa , Kenichi Kawaguchi
发明人： Osamu Nishijima , Shirou Yoshioka , Yukihiro Sasagawa , Kenichi Kawaguchi
IPC分类号： G06F9/00
CPC分类号： G06F15/7867
摘要： A configuration information storage section (108) stores configuration information for allowing a reconfigurable module to execute a predetermined function. A CPU (100) configures attached reconfigurable modules (103 to 106) according to the number thereof by referencing the configuration information stored in the configuration information storage section (108).
摘要翻译：配置信息存储部（108）存储用于允许可重构模块执行预定功能的配置信息。 CPU（100）通过参照存储在配置信息存储部（108）中的配置信息，根据其数量配置附加的可重配置模块（103〜106）。

5. 发明授权

US07287123B2 Cache memory, system, and method of storing data 有权
标题翻译：缓存存储器，系统和存储数据的方法
公开(公告)号：US07287123B2
公开(公告)日：2007-10-23
申请号：US11137560
申请日：2005-05-26
申请人： Shirou Yoshioka
发明人： Shirou Yoshioka
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/084 , G06F12/0842 , G06F12/0864
摘要： A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of the entry; the data attribute outputted from the processor; and the priority attribute of the first way, and (iii) an entry of a way other than the first way does not hold valid data, the entry being one of the entries that belong to the selected set, the control unit is further operable to store data into the entry of the way other than the first way.
摘要翻译：根据本发明的高速缓冲存储器是具有集合关联方案的高速缓冲存储器，包括：多个方式，每个方式由条目组成，每个条目保存数据和标签; 第一保持单元，用于以每一方式保存指示以该方式优先存储的数据类型的优先级属性; 第二保持单元，其至少以所述方式中的第一方式被包括，并且可操作地对于所述第一方式的每个条目保存指示保存在所述条目中的数据类型的数据属性; 以及控制单元，其可操作以通过对由所述第一保持单元保持的优先级属性与从处理器输出的数据属性相匹配的方式来对所述条目执行替换控制，其中当发生高速缓存未命中时，以及（i）有效数据在属于基于从处理器输出的地址选择的集合的条目之中的第一路径的条目中保存;（ii）所有以下属性都匹配：条目的数据属性; 从处理器输出的数据属性; 和所述第一方式的优先级属性，以及（iii）除了所述第一方式之外的方式的条目不保存有效数据，所述条目是属于所选集合的条目之一，所述控制单元还可操作为将数据存储到不同于第一种方式的条目中。

6. 发明授权

US07904675B2 Cache memory, system, and method of storing data 有权
标题翻译：缓存存储器，系统和存储数据的方法
公开(公告)号：US07904675B2
公开(公告)日：2011-03-08
申请号：US12498623
申请日：2009-07-07
申请人： Shirou Yoshioka
发明人： Shirou Yoshioka
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/084 , G06F12/0842 , G06F12/0864
摘要： A cache memory has a set associative scheme and includes a plurality of ways made up of entries, each entry holding data and a tag; a first holding unit holds, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit, included in a first way among the ways, holds, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit replaces control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein the control unit is further operable to store data into the entry of the way other than the first way.
摘要翻译：高速缓存存储器具有集合关联方案，并且包括由条目组成的多个方式，每个条目保持数据和标签; 第一保持单元以各种方式保存指示以该方式优先存储的数据类型的优先级属性; 以第一方式包含的第二保持单元，对于第一方式的每个条目，保持指示保存在该条目中的数据类型的数据属性; 并且控制单元通过对由第一保持单元保持的优先级属性与从处理器输出的数据属性相匹配的方式进行优先排序来替换对条目的控制，其中，所述控制单元还可操作以将数据存储到除第一路。

7. 发明授权

US07774281B2 Information contents download system 有权
标题翻译：信息内容下载系统
公开(公告)号：US07774281B2
公开(公告)日：2010-08-10
申请号：US11152085
申请日：2005-06-15
申请人： Minoru Okamoto , Katsuhiko Ueda , Shirou Yoshioka , Tetsuji Kishi
发明人： Minoru Okamoto , Katsuhiko Ueda , Shirou Yoshioka , Tetsuji Kishi
IPC分类号： G06F21/00
CPC分类号： G06F21/10
摘要： A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.
摘要翻译：终端装置向内容发布装置发送其设备信息和获取信息内容的请求。内容分发装置根据获取请求中指定的信息内容和设备信息生成分发用于实现终端装置中的信息内容的程序的请求，并发送使用实现功能所需的功能标准的许可请求到许可证管理设备。许可证管理装置接收使用许可证请求，并相应地向程序发布装置和内容分发装置发送使用功能标准的授权。程序分发装置仅在接收到使用授权时将程序发送到终端装置。内容分发装置仅在接收到使用授权时才将该信息内容发送到终端装置。

8. 发明授权

US07574572B2 Cache memory, system, and method of storing data 失效
标题翻译：缓存存储器，系统和存储数据的方法
公开(公告)号：US07574572B2
公开(公告)日：2009-08-11
申请号：US11898601
申请日：2007-09-13
申请人： Shirou Yoshioka
发明人： Shirou Yoshioka
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/084 , G06F12/0842 , G06F12/0864
摘要： A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of the entry; the data attribute outputted from the processor; and the priority attribute of the first way, and (iii) an entry of a way other than the first way does not hold valid data, the entry being one of the entries that belong to the selected set, the control unit is further operable to store data into the entry of the way other than the first way.
摘要翻译：根据本发明的高速缓冲存储器是具有集合关联方案的高速缓冲存储器，包括：多个方式，每个方式由条目组成，每个条目保存数据和标签; 第一保持单元，用于以每一方式保存指示以该方式优先存储的数据类型的优先级属性; 第二保持单元，其至少以所述方式中的第一方式被包括，并且可操作地对于所述第一方式的每个条目保存指示保存在所述条目中的数据类型的数据属性; 以及控制单元，其可操作以通过对由所述第一保持单元保持的优先级属性与从处理器输出的数据属性相匹配的方式来对所述条目执行替换控制，其中当发生高速缓存未命中时，以及（i）有效数据在属于基于从处理器输出的地址选择的集合的条目之中的第一路径的条目中保存;（ii）所有以下属性都匹配：条目的数据属性; 从处理器输出的数据属性; 和所述第一方式的优先级属性，以及（iii）除了所述第一方式之外的方式的条目不保存有效数据，所述条目是属于所选集合的条目之一，所述控制单元还可操作为将数据存储到不同于第一种方式的条目中。

9. 发明申请

US20050268041A1 Cache memory, system, and method of storing data 有权
标题翻译：缓存存储器，系统和存储数据的方法
公开(公告)号：US20050268041A1
公开(公告)日：2005-12-01
申请号：US11137560
申请日：2005-05-26
申请人： Shirou Yoshioka
发明人： Shirou Yoshioka
IPC分类号： G06F12/08 , G06F12/00 , G06F12/12
CPC分类号： G06F12/127 , G06F12/084 , G06F12/0842 , G06F12/0864
摘要： A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of the entry; the data attribute outputted from the processor; and the priority attribute of the first way, and (iii) an entry of a way other than the first way does not hold valid data, the entry being one of the entries that belong to the selected set, the control unit is further operable to store data into the entry of the way other than the first way.
摘要翻译：根据本发明的高速缓冲存储器是具有集合关联方案的高速缓冲存储器，包括：多个方式，每个方式由条目组成，每个条目保存数据和标签; 第一保持单元，用于以每一方式保存指示以该方式优先存储的数据类型的优先级属性; 第二保持单元，其至少以所述方式中的第一方式被包括，并且可操作地对于所述第一方式的每个条目保存指示保存在所述条目中的数据类型的数据属性; 以及控制单元，其可操作以通过对由所述第一保持单元保持的优先级属性与从处理器输出的数据属性相匹配的方式来对所述条目执行替换控制，其中，当发生高速缓存未命中时，以及（i）有效数据在属于基于从处理器输出的地址选择的集合的条目之中的第一路径的条目中保存;（ii）所有以下属性都匹配：条目的数据属性; 从处理器输出的数据属性; 和所述第一方式的优先级属性，以及（iii）除了所述第一方式之外的方式的条目不保存有效数据，所述条目是属于所选集合的条目之一，所述控制单元还可操作为将数据存储到不同于第一种方式的条目中。

10. 发明申请

US20100095096A1 AV DEVICE AND ITS CONTROL METHOD 审中-公开
标题翻译： AV设备及其控制方法
公开(公告)号：US20100095096A1
公开(公告)日：2010-04-15
申请号：US12526221
申请日：2008-06-27
申请人： Shirou Yoshioka
发明人： Shirou Yoshioka
IPC分类号： G06F9/30
CPC分类号： H04N5/85 , G11B27/34 , G11B2220/2562 , H04N5/765 , H04N21/42646 , H04N21/443
摘要： In an AV device control, from unit instructions (210, 220, 230) for executing a series of operations, input parts (211, 221, 231) for allowing user inputs to be inputted are respectively extracted and the extracted input parts (211, 221, 231) are concatenated as a first process, and execution parts (212, 222, 232) for operating the AV device according to the inputted user inputs are respectively extracted and the extracted execution parts (212, 222, 232) are concatenated as a second process. Then, the first process is arranged to be followed by the second process to constitute a macro instruction (240). In control using the macro instruction (240), after the user inputs required for executing the macro instruction are all inputted by the first process, the macro instruction by the second process is executed.
摘要翻译：在AV设备控制中，从用于执行一系列操作的单元指令（210,220,230）中分别提取用于允许输入用户输入的输入部分（211,221,231），并且提取的输入部分 221,231）被级联为第一处理，并且分别提取用于根据所输入的用户输入操作AV设备的执行部分（212,222,232），并且提取的执行部分（212,222,232）被级联为第二个过程。然后，第一处理被布置成随后是第二处理以构成宏指令（240）。在使用宏指令（240）的控制中，在通过第一处理全部输入执行宏指令所需的用户输入之后，执行第二处理的宏指令。

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